參數(shù)資料
型號: EDI416S4030A10SI
英文描述: 1Mx 16 Bits x 4 Banks Synchronous DRAM(100MHz,1M x 16 位 x 4 組同步動態(tài)RAM)
中文描述: 1Mx 16位× 4個銀行同步DRAM(100MHz的,100萬× 16位× 4個組同步動態(tài)RAM)的
文件頁數(shù): 18/26頁
文件大?。?/td> 353K
代理商: EDI416S4030A10SI
25
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI416S4030A
June 2000 Rev. 0
FIG. 16 MODE REGISTER SET CYCLE
FIG. 17 AUTO REFRESH CYCLE
RAS
CAS
ADDR
DQM
CKE
CLOCK
CE
Ra
Key
DQ
New Command
New
Command
Auto Refresh
MRS
WE
012
3
4
567
8
0
12
34
5
6
78
9
10
DON'T CARE
tRFC
HI-Z
Note 2
Note 1
Note 3
HIGH
NOTES:
Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
1. CE, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode
register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
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