參數(shù)資料
型號： DS3112+W
廠商： Maxim Integrated Products
文件頁數(shù)： 99/133頁
文件大?。?/td> 0K
描述： IC MUX T3/E3 3.3V 256-PBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 40
控制器類型： 調(diào)幀器，多路復(fù)用器
接口： 并行/串行
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 150mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-PBGA（27x27）
包裝： 管件
DS3112
68 of 133
6.4 T1/E1 AIS Generation Control Register Description
Via the T1/E1 Alarm Indication Signal (AIS) Control Registers, the host can configure the DS3112 to
generate an unframed all ones signal in either the transmit or receive paths on the 28 T1 ports or the 16/21
E1 ports. On reset, the device will force AIS in both the transmit and receive paths and it is up to the host
to modify the T1/E1 AIS Generation Control Registers to allow normal T1/E1 traffic to traverse the
DS3112. See the block diagrams in Section 1 for details on where the AIS signal is injected into the data
flow. When the M13/E13 multiplexer function is disabled in the DS3112 (see the UNCHEN control bit in
the Master Control Register 1 in Section 4.2 for details), the T1/E1 AIS Generation Control Registers are
meaningless and can be set to any value.
Register Name:
T1E1RAIS1
Register Description:
T1/E1 Receive Path AIS Generation Control Register 1
Register Address:
40h
Bit #
7
6
5
4
3
2
1
0
Name
AIS8
AIS7
AIS6
AIS5
AIS4
AIS3
AIS2
AIS1
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
AIS16
AIS15
AIS14
AIS13
AIS12
AIS11
AIS10
AIS9
Default
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15: Receive AIS Generation Control for T1/E1 Ports 1 to 16 (AIS1 to AIS2). These bits determine
whether the device will replace the demultiplexed T1/E1 data stream with an unframed all ones AIS signal. AIS1
controls the data at LRDAT1, AIS2 controls the data at LRDAT2, and so on. Since ports 4, 8, 12, 16, 20, 24, and
28 are not active in the G.747 mode, the AIS4, AIS8, AIS12, and AIS16 bits have no affect in the G.747 mode.
0 = send AIS to the LRDAT output
1 = send normal data to the LRDAT output
Register Name:
T1E1RAIS2
Register Description:
T1/E1 Receive Path AIS Generation Control Register 2
Register Address:
42h
Bit #
7
6
5
4
3
2
1
0
Name
AIS24
AIS23
AIS22
AIS21
AIS20
AIS19
AIS18
AIS17
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
—
AIS28
AIS27
AIS26
AIS25
Default
—
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 11:Receive AIS Generation Control for T1 Ports 17 to 28 (AIS17 to AIS28). These bits determine
whether the device will replace the demultiplexed T1/E1 data stream with an unframed all ones AIS signal. AIS17
controls the data at LRDAT17, AIS18 controls the data at LRDAT18, and so on. Since ports 17 to 28 are not active
in the E3 mode, these bits have no effect in the E3 mode. Since ports 4, 8, 12, 16, 20, 24, and 28 are not active in
the G.747 mode, the AIS20, AIS24 and AIS28 bits have no affect in the G.747 Mode.
0 = send AIS to the LRDAT output
1 = send normal data to the LRDAT output
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