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參數(shù)資料
| 型號(hào)： | DS3112+W |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 131/133頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MUX T3/E3 3.3V 256-PBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | 調(diào)幀器，多路復(fù)用器 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 150mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（27x27） |
| 包裝： | 管件 |
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DS3112
97 of 133
Bits 6 and 7: Transmit FEAC Codeword Select Bits 0 and 1 (TFS0 and TFS1). These two bits control what
two available codewords should be generated. Both TFS0 and TFS1 are edge triggered. To change the action, the
host must go back to the null state (TFS0 = TFS1 = 0) before proceeding to the desired action. Wait a minimum of
(10) codewords before changing to out-of-idle state.
TFS1
TFS0
ACTION
0
Idle state; do not generate a FEAC codeword (send all ones)
0
1
Send 10 of codeword A followed by all ones
1
0
Send 10 of codeword A followed by 10 of codeword B followed by all ones
1
Send codeword A continuously (will be sent for at least 10 times)
Bits 8 to 13: Transmit FEAC Codeword B Data (TFCB0 to TFCB5). The FEAC codeword is of the form
...0xxxxxx011111111... where the rightmost bit is transmitted first. These six bits are the middle six bits of the
second byte of the FEAC codeword (i.e., the six “x” bits). The device can generate two different codewords and
these six bits represent what will be transmitted for codeword B. TFCB0 is the LSB and is transmitted first while
TFCB5 is the MSB and is transmitted last. The TFS0 and TFS1 control bits determine if this codeword is to be
generated. These bits should only be changed when the transmit FEAC controller is in the idle state (TFS0 = 0 and
TFS1 = 0).
Bit 14: Interrupt Enable, Receive FEAC Idle (IERFI). This bit masks or enables interrupts caused by the
Receive FEAC Idle (RFI) bit in the FSR register.
0 = interrupt masked
1 = interrupt unmasked
Bit 15: Receive FEAC Controller Reset (RFR). A zero to one transition will reset the receive FEAC controller
and flush the Receive FEAC FIFO. This bit must be cleared and set again for a subsequent reset.
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