參數(shù)資料
型號： DS3112+W
廠商： Maxim Integrated Products
文件頁數(shù)： 45/133頁
文件大?。?/td> 0K
描述： IC MUX T3/E3 3.3V 256-PBGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 40
控制器類型： 調(diào)幀器，多路復用器
接口： 并行/串行
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 150mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應商設備封裝： 256-PBGA（27x27）
包裝： 管件
DS3112
19 of 133
2.2 CPU Bus Signal Description
Signal Name:
CMS
Signal Description:
CPU Bus Mode Select
Signal Type:
Input
This signal should be tied low when the device is to be operated as a 16-bit bus. This signal should be tied
high when the device is to be operated as an 8-bit bus.
0 = CPU Bus is in the 16-Bit Mode
1 = CPU Bus is in the 8-Bit Mode
Signal Name:
CIM
Signal Description:
CPU Bus Intel/Motorola Bus Select
Signal Type:
Input
The signal determines whether the CPU Bus will operate in the Intel Mode (CIM = 0) or the Motorola
Mode (CIM = 1). The signal names in parentheses are operational when the device is in the Motorola
Mode.
0 = CPU Bus is in the Intel Mode
1 = CPU Bus is in the Motorola Mode
Signal Name:
CD0 to CD15
Signal Description:
CPU Bus Data Bus
Signal Type:
Input/Output (Tri-State Capable)
The external host will configure the device and obtain real-time status information about the device via
these signals. When reading data from the CPU Bus, these signals will be outputs. When writing data to
the CPU Bus, these signals will become inputs. When the CPU bus is operated in the 8-bit mode
(CMS = 1), CD8 to CD15 are inactive and should be tied low.
Signal Name:
CA0 to CA7
Signal Description:
CPU Bus Address Bus
Signal Type:
Input
These input signals determine which internal device configuration register that the external host wishes to
access. When the CPU bus is operated in the 16-bit mode (CMS = 0), CA0 is inactive and should be tied
low. When the CPU bus is operated in the 8-bit mode (CMS = 1), CA0 is the least significant address bit.
Signal Name:
CWR (CR/W)
Signal Description:
CPU Bus Write Enable (CPU Bus Read/Write Select)
Signal Type:
Input
In Intel Mode (CIM = 0), this signal will determine when data is to be written to the device. In Motorola
Mode (CIM = 1), this signal will be used to determine whether a read or write is to occur.
Signal Name:
CRD (CDS)
Signal Description:
CPU Bus Read Enable (CPU Bus Data Strobe)
Signal Type:
Input
In Intel Mode (CIM = 0) this signal will determine when data is to be read from the device. In Motorola
Mode (CIM = 1), a rising edge will be used to write data into the device.
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