參數(shù)資料
型號: DS3112+W
廠商: Maxim Integrated Products
文件頁數(shù): 40/133頁
文件大小: 0K
描述: IC MUX T3/E3 3.3V 256-PBGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: 調(diào)幀器,多路復(fù)用器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 150mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-PBGA(27x27)
包裝: 管件
DS3112
14 of 133
2
PIN DESCRIPTION
This section describes the input and output signals on the DS3112. Signal names follow a convention that
is shown in Table 2-1. Table 2-2 lists all the signals, their signal type, description, and pin location.
Table 2-1. Pin Naming Convention
FIRST
LETTERS
SIGNAL CATEGORY
SECTION
C
CPU/Host Control Access Port
FR
T3/E3 Receive Framer
FT
T3/E3 Transmit Formatter
LR
Low-Speed (T1 or E1) Receive Port
LT
Low-Speed (T1 or E1) Transmit Port
HR
High-Speed (T3 or E3) Receive Port
HT
High-Speed (T3 or E3) Transmit Port
J
JTAG Test Port
Table 2-2. Pin Description
PIN
NAME
TYPE
FUNCTION
C7
CALE
I
CPU Bus Address Latch Enable
H3
CA0
I
CPU Bus Address Bit 0 (LSB)
H2
CA1
I
CPU Bus Address Bit 1
H1
CA2
I
CPU Bus Address Bit 2
J4
CA3
I
CPU Bus Address Bit 3
J3
CA4
I
CPU Bus Address Bit 4
J2
CA5
I
CPU Bus Address Bit 5
J1
CA6
I
CPU Bus Address Bit 6
K2
CA7
I
CPU Bus Address Bit 7 (MSB)
C4
CCS
I
CPU Bus Chip Select (Active Low)
C2
CD0
I/O
CPU Bus Data Bit 0 (LSB)
D2
CD1
I/O
CPU Bus Data Bit 1
D3
CD2
I/O
CPU Bus Data Bit 2
E4
CD3
I/O
CPU Bus Data Bit 3
C1
CD4
I/O
CPU Bus Data Bit 4
D1
CD5
I/O
CPU Bus Data Bit 5
E3
CD6
I/O
CPU Bus Data Bit 6
E2
CD7
I/O
CPU Bus Data Bit 7
E1
CD8
I/O
CPU Bus Data Bit 8
F3
CD9
I/O
CPU Bus Data Bit 9
G4
CD10
I/O
CPU Bus Data Bit 10
F2
CD11
I/O
CPU Bus Data Bit 11
F1
CD12
I/O
CPU Bus Data Bit 12
G3
CD13
I/O
CPU Bus Data Bit 13
G2
CD14
I/O
CPU Bus Data Bit 14
G1
CD15
I/O
CPU Bus Data Bit 15 (MSB)
B3
CIM
I
CPU Bus Intel/Motorola Bus Select, 0 = Intel, 1 = Motorola
A2
CINT
O
CPU Bus Interrupt
B2
CMS
I
CPU Bus Mode Select, 0 = 16 Bit, 1 = 8 Bit Mode
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