參數(shù)資料
型號(hào)： DS3112+W
廠商： Maxim Integrated Products
文件頁數(shù)： 107/133頁
文件大小： 0K
描述： IC MUX T3/E3 3.3V 256-PBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 40
控制器類型： 調(diào)幀器，多路復(fù)用器
接口： 并行/串行
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 150mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-PBGA（27x27）
包裝： 管件
DS3112
75 of 133
7.6 T1 Line Loopback Command Status Register Description
Register Name:
T1LBSR1
Register Description:
T1 Line Loopback Command Status Register 1
Register Address:
5Ch
Bit #
7
6
5
4
3
2
1
0
Name
LLB8
LLB7
LLB6
LLB5
LLB4
LLB3
LLB2
LLB1
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
LLB16
LLB15
LLB14
LLB13
LLB12
LLB11
LLB10
LLB9
Default
—
Note: See Figure 7-1 for details on the signal flow for the status bits in the T1LBSR1 and T1LBSR2 registers. Bits that are underlined are
read-only; all other bits are read-write.
Bits 0 to 15: T1 Line Loopback Command Status for Ports 1 to 16 (LLB1 to LLB16). These read-only real-
time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is the inverse of the
C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the C3 bit is not the inverse of
the C1 and C2 bits for five consecutive frames. LLB1 corresponds to T1/E1 Port 1, LLB2 corresponds to T1/E1
Port 2, and so on. The setting of any of the bits in T1LBSR1 or T1LBSR2 can cause a hardware interrupt to occur
if the T1LB bit in the Interrupt Mask for MSR (IMSR) is set to a one. In the E3 and G.747 modes, these bits are
meaningless and should be ignored.
Register Name:
T1LBSR2
Register Description:
T1 Line Loopback Command Status Register 2
Register Address:
5Eh
Bit #
7
6
5
4
3
2
1
0
Name
LLB24
LLB23
LLB22
LLB21
LLB20
LLB19
LLB18
LLB17
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
—
LLB28
LLB27
LLB26
LLB25
Default
—
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 11: T1 Line Loopback Command Status for Ports 17 to 28 (LLB17 to LLB28). These read-only real-
time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is the inverse of the
C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the C3 bit is not the inverse of
the C1 and C2 bits for five consecutive frames. LLB17 corresponds to T1/E1 Port 17, LLB18 corresponds to T1/E1
Port 18, and so on. The setting of any of the bits in T1LBSR1 or T1LBSR2 can cause a hardware interrupt to occur
if the T1LB bit in the Interrupt Mask for MSR (IMSR) is set to a one. In the E3 and G.747 Modes, these bits are
meaningless and should be ignored.
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