參數(shù)資料
型號： DS3112+W
廠商： Maxim Integrated Products
文件頁數(shù)： 59/133頁
文件大?。?/td> 0K
描述： IC MUX T3/E3 3.3V 256-PBGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 40
控制器類型： 調(diào)幀器，多路復(fù)用器
接口： 并行/串行
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 150mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-PBGA（27x27）
包裝： 管件
DS3112
31 of 133
3
MEMORY MAP
Table 3-1. Memory Map
ADDRESS
ACRONYM
R/W
REGISTER NAME
SECTION
00
MRID
R/W
Master Reset and ID Register
02
MC1
R/W
Master Configuration Register 1
04
MC2
R/W
Master Configuration Register 2
06
MC3
R/W
Master Configuration Register 3
08
MSR
R
Master Status Register
0A
IMSR
R/W
Interrupt Mask Register for MSR
0C
TEST
R/W
Test Register
10
T3E3CR
R/W
T3/E3 Control Register
12
T3E3SR
R
T3/E3 Status Register
14
IT3E3SR
R/W
Interrupt Mask for T3E3SR
16
T3E3INFO
R
T3/E3 Information Register
18
T3E3EIC
R/W
T3/E3 Error Insert Control Register
20
BPVCR
R
T3/E3 Bipolar Violation (BPV) Count Register
22
EXZCR
R
T3/E3 Excessive Zero (EXZ) Count Register
24
FECR
R
T3/E3 Frame Error Count Register
26
PCR
R
T3 Parity Bit Error Count Register
28
CPCR
R
T3 C-Bit Parity Error Count Register
2A
FEBECR
R
T3 Far End Block Error or E3 RAI Count Register
30
T2E2CR1
R/W
T2/E2 Control Register 1
32
T2E2CR2
R/W
T2/E2 Control Register 2
34
T2E2SR1
R/W
T2/E2 Status Register 1
36
T2E2SR2
R/W
T2/E2 Status Register 2
40
T1E1RAIS1
R/W
T1/E1 Receive Path AIS Generation Control Register 1
42
T1E1RAIS2
R/W
T1/E1 Receive Path AIS Generation Control Register 2
44
T1E1TAIS1
R/W
T1/E1 Transmit Path AIS Generation Control Register 1
46
T1E1TAIS2
R/W
T1/E1 Transmit Path AIS Generation Control Register 2
50
T1E1LLB1
R/W
T1/E1 Line Loopback Control Register 1
52
T1E1LLB2
R/W
T1/E1 Line Loopback Control Register 2
54
T1E1DLB1
R/W
T1/E1 Diagnostic Loopback Control Register 1
56
T1E1DLB2
R/W
T1/E1 Diagnostic Loopback Control Register 2
58
T1LBCR1
R/W
T1 Line Loopback Command Register 1
5A
T1LBCR2
R/W
T1 Line Loopback Command Register 2
5C
T1LBSR1
R
T1 Line Loopback Status Register 1
5E
T1LBSR2
R
T1 Line Loopback Status Register 2
60
T1E1SDP
R/W
T1/E1 Select Register for Receive Drop Ports A and B
62
T1E1SIP
R/W
T1/E1 Select Register for Transmit Drop Ports A and B
6E
BERTMC
R/W
BERT Mux Control Register
70
BERTC0
R/W
BERT Control 0
72
BERTC1
R/W
BERT Control 1
74
BERTRP0
R/W
BERT Repetitive Pattern Set 0 (lower word)
76
BERTRP1
R/W
BERT Repetitive Pattern Set 1 (upper word)
78
BERTBC0
R
BERT Bit Counter 0 (lower word)
7A
BERTBC1
R
BERT Bit Counter 1 (upper word)
7C
BERTEC0
R
BERT Error Counter 0 (lower word)
7E
BERTEC1
R
BERT Error Counter 1 (upper word)
80
HCR
R/W
HDLC Control Register
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