- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11562 > DS3112+W (Maxim Integrated Products)IC MUX T3/E3 3.3V 256-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | DS3112+W |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 80/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX T3/E3 3.3V 256-PBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | 調(diào)幀器，多路復(fù)用器 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 150mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（27x27） |
| 包裝： | 管件 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)當(dāng)前第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
DS3112
50 of 133
Bit 7: T3/E3 Diagnostic Loopback Enable (DLB). See Figure 1-1 and Figure 1-2 for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
Bit 8: E3 Code Violation Enable (E3CVE). This bit is ignored in the T3 mode. This bit is used in the E3 mode to
configure the BiPolar Violation Count Register (BPVCR) to count either BiPolar Violations (BPV) or Code
Violations (CV). A BPV is defined as consecutive pulses (or marks) of the same polarity that are not part of a
HDB3 codeword. A CV is defined in ITU O.161 as consecutive BPVs of the same polarity.
0 = count BPV
1 = count CV
Bits 9 and 10: T3/E3 Frame Error Counting Control Bits 0 and 1 (FECC0 and FECC1).
FECC1
FECC0
FRAME ERROR COUNT REGISTER (FECR) CONFIGURATION
0
T3 Mode: Count Loss Of Frame (LOF) Occurrences
E3 Mode: Count Loss Of Frame (LOF) Occurrences
0
1
T3 Mode: Count Both F Bit and M Bit Errors
E3 Mode: Count Bit Errors in the FAS Word
1
0
T3 Mode: Count Only F Bit Errors
E3 Mode: Count Word Errors in the FAS Word
1
T3 Mode: Count Only M Bit Errors
E3 Mode: Illegal State
Bit 11: Error Counting Control (ECC). This bit is used to control whether the device will increment the error
counters during Loss Of Frame (LOF) conditions. It only affects the error counters that count errors that are based
on framed information and these include the following:
Frame Error Counter (when it is configured to count frame errors, not LOF occurrences)
T3 Parity Bit Error Counter
T3 C-Bit Parity Error Counter
T3 Far End Block Error or E3 RAI Counter
When this bit is set low, these error counters will not be allowed to increment during LOF conditions. When this bit
is set high, these error counters will be allowed to increment during LOF conditions.
0 = stop the FECR/PCR/CPCR/FEBECR error counters from incrementing during LOF
1 = allow the FECR/PCR/CPCR/FEBECR error counters to increment during LOF
Bit 12: Automatic FEBE Defeat (AFEBED). This bit is ignored in the E3 mode and in the T3 mode when the
device is not configured in the C-Bit Parity Mode. When this bit is low, the device will automatically insert the
FEBE codes into the transmitted data stream by setting all three C bits in Subframe 4 to zero.
0 = automatically insert FEBE codes in the transmit data stream based on detected errors
1 = use the TFEBE control to determine the state of the FEBE codes
Bit 13: Transmit FEBE Setting (TFEBE). This bit is only active when AFEBED is active (i.e., AFEBED = 1).
When this bit is low, the device will force the FEBE code to 111 continuously. When this bit is set high, the device
will force the FEBE code to 000 continuously.
0 = force FEBE to 111 (null state)
1 = force FEBE to 000 (active state)
Bit 14: T3/E3 Payload Loopback Enable (PLB). See Figure 1-1 and Figure 1-2 for a visual description of this
loopback.
0 = disable loopback
1 = enable loopback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CONREVSMA007-R58 | CONN RP-SMA MALE END CRIMP RG-58 |
| DS26401NA2+ | IC OCTAL FRAMER T1/E1/J1 256BGA |
| VI-24L-IX-S | CONVERTER MOD DC/DC 28V 75W |
| DS26401+ | IC OCTAL FRAMER T1/E1/J1 256BGA |
| PIC16LF1938-E/SS | MCU 8BIT 16K FLASH 28SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3116MP000 | 制造商:Thomas & Betts 功能描述:MAXGARD - RR8F |
| DS311X | 功能描述:KWIK-CHG DESIGNATION STRIPS DBL RoHS:是 類別:盒，外殼，支架 >> 插線臺(tái)，插座面板 - 配件 系列:Kwik-Change® 標(biāo)準(zhǔn)包裝:50 系列:- 附件類型:模擬插頭，雙 樣式:耳機(jī)，0.173" 直徑 包括:- |
| DS312 | 功能描述:插線板 DESIGN STRIP COVER RoHS:否 制造商:Switchcraft 產(chǎn)品類型:Bantam (TT) 正規(guī)化: 高度/機(jī)架數(shù)量: 深度: 端接類型: 位置/觸點(diǎn)數(shù)量:48 |
| DS-312 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Four-Way Power Divider, 10 - 500 MHz |
| DS312_09 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-3E FPGA Family: Introduction and Ordering Information |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。