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參數資料
| 型號： | DS3112+W |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 48/133頁 |
| 文件大小： | 0K |
| 描述： | IC MUX T3/E3 3.3V 256-PBGA |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 40 |
| 控制器類型： | 調幀器，多路復用器 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 150mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應商設備封裝： | 256-PBGA（27x27） |
| 包裝： | 管件 |
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DS3112
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2.3 T3/E3 Receive Framer Signal Description
Signal Name:
FRSOF
Signal Description:
T3/E3 Receive Framer Start Of Frame Sync Signal
Signal Type:
Output
This signal pulses for one FRCLK period to indicate the T3 or E3 frame boundary (Figure 2-1). This
signal can be configured via the FRSOFI control bit in Master Control Register 3 (Section 4.2) to be
either active high (normal mode) or active low (inverted mode).
Signal Name:
FRCLK
Signal Description:
T3/E3 Receive Framer Clock
Signal Type:
Output
This signal outputs the clock that is used to pass data through the receive T3/E3 framer. It can be sourced
from either the HRCLK or FTCLK inputs (Figure 1-1 and Figure 1-2). This signal is used to clock the
receive data out of the device at the FRD output. Data can be either updated on a rising edge (normal
mode) or a falling edge (inverted mode). This option is controlled via the FRCLKI control bit in Master
Control Register 3 (Section 4.3).
Signal Name:
FRD
Signal Description:
T3/E3 Receive Framer Serial Data
Signal Type:
Output
This signal outputs data from the receive T3/E3 framer. This signal is updated either on the rising edge of
FRCLK (normal mode) or the falling edge of FRCLK (inverted mode). This option is controlled via the
FRCLKI control bit in Master Control Register 3 (Section 4.3). Also, this signal can be internally inverted
if enabled via the FRDI control bit in Master Control Register 3 (Section 4.3).
Signal Name:
FRDEN
Signal Description:
T3/E3 Receive Framer Serial Data Enable or Gapped Clock Output
Signal Type:
Output
Via the DENMS control bit in Master Control Register 1, this signal can be configured to either output a
data enable or a gapped clock. In the data enable mode, this signal will go active when payload data is
available at the FRD output and it will go inactive when overhead data is being output at the FRD output.
In the gapped clock mode, this signal will transition for each bit of payload data and will be suppressed
for each bit of overhead data. In the T3 Mode, overhead data is defined as the M Bits, F Bits, C Bits, X
Bits, and P Bits. In the E3 Mode, overhead data is defined as the FAS word, RAI Bit and Sn Bit (i.e., bits
1 to 12). See Figure 2-1 for an example. This signal can be internally inverted if enabled via the FRDENI
control bit in Master Control Register 3 (Section 4.3).
Signal Name:
FRMECU
Signal Description:
T3/E3 Receive Framer Manual Error Counter Update Strobe
Signal Type:
Input
Via the AECU control bit in Master Control Register 1 (Section 4.3), the DS3112 can be configured to
use this asynchronous input to initiate an updating of the internal error counters. A zero to one transition
on this input causes the device to begin loading the internal error counters with the latest error counts.
This signal must be returned low before a subsequent updating of the error counters can occur. The host
must wait at least 100ns before reading the error counters to allow the device time to update the error
counters. This signal is logically ORed with the MECU control bit in Master Control Register 1. If this
signal is not used, then it should be tied low.
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