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參數(shù)資料
| 型號(hào)： | DS3112+W |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 87/133頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX T3/E3 3.3V 256-PBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | 調(diào)幀器，多路復(fù)用器 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 150mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（27x27） |
| 包裝： | 管件 |
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DS3112
57 of 133
Table 5-2. E3 Alarm Criteria
ALARM/
CONDITION
DEFINITION
SET CRITERIA
CLEAR CRITERIA
AIS
Alarm Indication Signal
Unframed all ones
Four or fewer zeros in
two consecutive 1536-
bit frames
Five or more zeros in two
consecutive 1536-bit frames
LOS
Loss Of Signal
(See note)
192 consecutive zeros
No EXZ events over a 192-bit
window that starts with the
first one received
LOF
Loss Of Frame
Too many FAS errors
Four consecutive bad
FAS
Three consecutive good FAS
RAI
Remote Alarm Indication
Inactive: Bit 11 of the frame = 0
Active: Bit 11 of the frame = 1
Bit 11 = 1 for 4
consecutive frames
(6144 bits/179s)
Bit 11 = 0 for 4 consecutive
frames (6144 bits/179s)
Note: LOS is not defined for unipolar (binary) operation.
Register Name:
T3E3INFO
Register Description:
T3/E3 Information Register
Register Address:
16h
Bit #
7
6
5
4
3
2
1
0
Name
—
SEFE
EXZ
MBE
FBE
ZSCD
COFA
Default
—
Bit #
15
14
13
12
11
10
9
8
Name
—
RAIC
AISC
LOFC
LOSC
T3AIC
E3Sn
Default
—
Note: Bits that are underlined are read-only; all other bits are read-write. The status bits in the T3E3INFO cannot cause a hardware
interrupt to occur.
Bit 0: Change Of Frame Alignment Detected (COFA). This latched read-only event-status bit will be set to a
one when the T3/E3 framer has experienced a change of frame alignment (COFA). A COFA occurs when the
device achieves synchronization in a different alignment than it had previously. If the device has never acquired
synchronization before, then this status bit is meaningless. This bit will be cleared when read and will not be set
again until the framer has lost synchronization and reacquired synchronization in a different alignment.
Bit 1: Zero Suppression Codeword Detected (ZSCD). This latched read-only event-status bit will be set to a one
when the T3/E3 framer has detected a B3ZS/HDB3 codeword. This bit will be cleared when read and will not be
set again until the framer has detected another B3ZS/HDB3 codeword.
Bit 2: F-Bit or FAS Error Detected (FBE). This latched read-only status bit will be set to a one when the DS3112
has detected an error in either the F bits (T3 mode) or the FAS word (E3 mode). This bit will be cleared when read
and will not be set again until the device detects another error.
Bit 3: M-Bit Error Detected (MBE). This latched read-only event status bit will be set to a one when the DS3112
has detected an error in the M bits. This bit will be cleared when read and will not be set again until the device
detects another error in one of the M bits. This status bit has no meaning in the E3 mode and should be ignored.
Bit 4: Excessive Zeros Detected (EXZ). This latched read-only event status bit will be set to a one each time the
DS3112 has detected a consecutive string of either three or more zeros (T3 mode) or four or more zeros (E3 mode).
This bit will be cleared when read and will not be set again until the device detects another EXcessive Zero event.
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