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參數(shù)資料
| 型號(hào)： | DS3112+W |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 130/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX T3/E3 3.3V 256-PBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 控制器類型： | 調(diào)幀器，多路復(fù)用器 |
| 接口： | 并行/串行 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 電流 - 電源： | 150mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（27x27） |
| 包裝： | 管件 |
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DS3112
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10 FEAC CONTROLLER
The DS3112 contains an onboard FEAC controller. When the device is operated in the T3 mode, the
FEAC controller is only active in the C-Bit Parity Mode. When the device is operated in the E3 mode, the
user has the option to connect the FEAC controller to the Sn bit position. On the receive side, the FEAC
controller is always connected to the receive E3 framer. If the host does not wish to use the FEAC
controller for the Sn bit, then the status updates provided by the FEAC controller are ignored. On the
transmit side, the host selects the source of the Sn via the E3SnC0 and E3SnC1 controls bits in the T3/E3
Control Register (Section 5.2).
The DS3112 can both detect and generate Far End Alarm Codewords (FEAC). The FEAC codeword is a
repeating 16 bit pattern of the form ...0xxxxxx011111111... where the rightmost bit is transmitted first.
The FEAC codeword must be transmitted at least 10 times. When no FEAC codeword is being
transmitted, the data pattern should be forced to all ones.
The receive FEAC detector does a bit by bit search for a data pattern of the form of a FEAC codeword.
Once found, the receive FEAC detector validates incoming codewords by checking to see that the same
codeword is found in three consecutive opportunities. Once validated, a codeword is considered no longer
present when it is received incorrectly twice in a row. Once a codeword is validated, the Receive FEAC
Codeword Detect (RFCD) status bit is set and the codeword is written into the Receive FEAC FIFO for
the host to read. The host can use the RFCD status to know when to read the Receive FEAC FIFO. The
Receive FEAC FIFO is four codewords deep. If the FIFO is full when the receive FEAC detector
attempts to write a new incoming codeword, the latest incoming codeword(s) will be discarded and the
Receive FEAC FIFO Overflow (RFFO) status bit will be set.
90h
The DS3112 can transmit two different FEAC codewords. This is useful if the host wishes to generate a
Loopback Command which is made up of 10 FEAC codewords that indicate the type of loopback
followed by 10 FEAC codewords that indicate which line is to be looped back.
10.1 FEAC Control Register Description
Register Name:
FCR
Register Description:
FEAC Control Register
Register Address:
Bit #
7
6
5
4
3
2
1
0
Name
TFS1
TFS0
TFCA5
TFCA4
TFCA3
TFCA2
TFCA1
TFCA0
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
RFR
IERFI
TFCB5
TFCB4
TFCB3
TFCB2
TFCB1
TFCB0
Default
0
—
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 5: Transmit FEAC Codeword A Data (TFCA0 to TFCA5). The FEAC codeword is of the form
...0xxxxxx011111111... where the rightmost bit is transmitted first. These six bits are the middle six bits of the
second byte of the FEAC codeword (i.e., the six “x” bits). The device can generate two different codewords and
these six bits represent what will be transmitted for codeword A. TFCA0 is the LSB and is transmitted first while
TFCA5 is the MSB and is transmitted last. The TFS0 and TFS1 control bits determine if this codeword is to be
generated. These bits should only be changed when the transmit FEAC controller is in the idle state (TFS0 = 0 and
TFS1 = 0).
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