參數(shù)資料
型號： DS3112+W
廠商： Maxim Integrated Products
文件頁數(shù)： 122/133頁
文件大小： 0K
描述： IC MUX T3/E3 3.3V 256-PBGA
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 40
控制器類型： 調(diào)幀器，多路復用器
接口： 并行/串行
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 150mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-PBGA（27x27）
包裝： 管件
DS3112
89 of 133
Bit 5: Transmit HDLC Reset (THR). A zero to one transition will reset the Transmit HDLC controller. Must be
cleared and set again for a subsequent reset. A reset will flush the current contents of the transmit FIFO and cause
one FEh abort sequence (7 ones is a row) to be sent followed by either 7Eh (flags) or FFh (idle) until a new packet
is initiated by writing new data (at least 2 bytes) into the FIFO.
Bit 6: Receive HDLC Reset (RHR). A zero to one transition will reset the Receive HDLC controller. Must be
cleared and set again for a subsequent reset. A reset will flush the current contents of the receive FIFO and cause
the receive HDLC controller to begin searching for a new incoming HDLC packet.
Bit 8: Transmit Invert Data (TID). The control bit determines whether all of the data from the HDLC controller
(including flags and CRC checksum) will be inverted after processing.
0 = do not invert data (normal operation)
1 = invert all data
Bit 9: Receive Invert Data (RID). The control bit determines whether all of the data into the HDLC controller
(including flags and CRC checksum) will be inverted before processing.
0 = do not invert data (normal operation)
1 = invert all data
Bits 10 to 12: Transmit Low Watermark Select Bits (TLWMS0 to TLWMS2). These control bits determine
when the HDLC controller should set the TLWM status bit in the HDLC Status Register (HSR). When the transmit
FIFO contains less than the number of bytes configured by these bits, the TLWM status bit will be set to a one.
TLWMS2
TLWMS1
TLWMS0
TRANSMIT LOW
WATERMARK (bytes)
0
16
0
1
48
0
1
0
80
0
1
112
1
0
144
1
0
1
176
1
0
208
1
240
Bits 13 to 15: Receive High Watermark Select Bits (RHWMS0 to RHWMS2). These control bits determine
when the HDLC controller should set the RHWM status bit in the HDLC Status Register (HSR). When the receive
FIFO contains more than the number of bytes configured by these bits, the RHWM status bit will be set to a one.
RHWMS2
RHWMS1
RHWMS0
RECEIVE HIGH
WATERMARK (bytes)
0
16
0
1
48
0
1
0
80
0
1
112
1
0
144
1
0
1
176
1
0
208
1
240
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