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| 型號(hào)： | CYNSE70064A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Search Engine |
| 中文描述： | 搜索引擎 |
| 文件頁數(shù)： | 99/127頁 |
| 文件大?。?/td> | 3275K |
| 代理商： | CYNSE70064A |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 99 of 127
11.2
Figure 11-2
shows how to cascade up to four blocks. Each block contains up to eight CYNSE70064A devices except the last,
and the interconnection within each was shown in the previous subsection with the cascading of up to eight devices in a block.
Note
. The interconnection between blocks for depth-cascading is important. For each Search, a block asserts BHO[2], BHO[1],
and BHO[0]. The BHO[2:0] signals for a block are the signals taken only from the last device in the block. For all other devices
within that block, these signals stay open and floating. The host ASIC must program the table size (TLSZ) field to 10 in each of
the devices for cascading up to 31 devices (in up to four blocks).
Depth-Cascading up to 31 Devices (Four Blocks)
11.3
Bit[0] of each of the 68-bit entries is designated as a special bit (1 = occupied; 0 = empty). For each Learn or PIO Write to the
data array, each device asserts FULO[1] and FULO[0] if it does not have any empty locations within it (see
Figure 11-3
). Each
device combines the FULO signals from the devices above it with its own full status to generate a FULL signal that gives the full
status of the table up to the device asserting the FULL signal.
Figure 11-3
shows the hardware connection diagram for generating
the FULL signal that goes back to the ASIC. In a depth-cascaded block of up to eight devices, the FULL signal from the last device
should be fed back to the ASIC controller to indicate the fullness of the table. The FULL signal of the other devices should be left
open.
Note
. The Learn instruction is supported for only up to eight devices, whereas FULL cascading is allowed only for one
block in tables containing more than eight devices. In tables for which a Learn instruction is not going to be used, the bit[0] of
each 68-bit entry should always be set to 1.
Depth-Cascading for a FULL Signal
BHO[2]
Block of 8
CYNSE70064As
Block 0 (devices 0–7)
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
BHI[2]
Block of 7
CYNSE70064As
Block 3 (devices 24-30)
BHO[2]
BHO[1]
BHI[1]
BHI[0]
GND
BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8
CYNSE70064As
Block 1 (devices 8–15)
BHO[2]
Block of 8
CYNSE70064As
Block 2 (devices 16–23)
BHO[2]
BHO[1]
DQ[67:0]
CMD[8:0], CMDV
SRAM
BHO[1]
BHO[0]
BHO[0]
SSF, SSV
Figure 11-2. Depth-Cascading Four Blocks
相關(guān)PDF資料 |
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| CYNSE70064A-50BGC | Search Engine |
| CYNSE70064A-66BGC | Search Engine |
| CYNSE70064A-83BGC | Search Engine |
| CYP15G0101DXA | Single Channel HOTLink II Transceiver |
| CYP15G0101DXA-BBI | Single Channel HOTLink II Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYNSE70064A-50BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70064A-66BG | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70064A-66BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70064A-83BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Network Processing |
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