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| 型號(hào)： | CYNSE70064A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Search Engine |
| 中文描述： | 搜索引擎 |
| 文件頁(yè)數(shù)： | 93/127頁(yè) |
| 文件大?。?/td> | 3275K |
| 代理商： | CYNSE70064A |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 93 of 127
Figure 10-72
shows the sample table. Two bits in each 68-bit entry will need to designated as the table number bits. One example
choice can be the 00 values for the table configured as ×68, 01 values for tables configured as ×136, and 10 values for tables
configured as ×272. For the above explanation, it is further assumed that bits [67:66] for each entry will be designed as such table
designation bits.
cycle
1
2
3
4
10.16
When search engines are cascaded using multiple CYNSE70064As, the SADR, CE_L, and WE_L (three-state signals) are all
tied together. In order to eliminate external pull-ups and pull-downs, one device in a bank is designated as the default driver. For
non-Search or non-Learn cycles (see Subsection 10.17, “Learn Command” on page 94) or Search cycles with a global miss, the
SADR, CE_L, and WE_L signals are driven by the device with the LRAM bit set. It is important that only one device in a bank of
search engines that are cascaded have this bit set. Failure to do so will cause contention on SADR, CE_L, and WE_L and can
potentially cause damage to the device(s).
LRAM and LDEV Description
CLK2X
CMDV
CMD[1:0]
CE_L
OE_L
Hit
Hit
CMD[8:2]
WE_L
cycle
cycle
cycle
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
CFG = 1010101010101010, HLAT = 010, TLSZ = 00, LRAM = 1, LDEV = 1.
PHS_L
SADR[21:0]
SSF
SSV
ALE_L
Se×68
A2
01
01
Search1
Search3
A B A B A B A B
0
0
1
1
0
0
1
1
0
1
1
0
A B A B A B C D
D1
D2
DQ
D3
CMD[2]
1
0
1
0
1
A3
Search2
01
1
1
0
0
0
0
1
0
1
×136
Hit
S ×272
A1
Figure 10-71. Timing Diagram for Mixed Search (One Device)
2 K
16 K
68
4 K
136
272
CFG = 10010000
Figure 10-72. Multiwidth Configurations Example
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYNSE70064A-50BGC | Search Engine |
| CYNSE70064A-66BGC | Search Engine |
| CYNSE70064A-83BGC | Search Engine |
| CYP15G0101DXA | Single Channel HOTLink II Transceiver |
| CYP15G0101DXA-BBI | Single Channel HOTLink II Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYNSE70064A-50BGC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70064A-66BG | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70064A-66BGC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70064A-83BGC | 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70128 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Network Processing |
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