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| 型號： | CYNSE70064A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Search Engine |
| 中文描述： | 搜索引擎 |
| 文件頁數(shù)： | 109/127頁 |
| 文件大?。?/td> | 3275K |
| 代理商： | CYNSE70064A |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 109 of 127
12.7
The following explains the SRAM Write operation done through a table(s) of up to eight devices with the following parameters
(TLSZ = 01). The diagram of such a table is shown in
Figure 12-9
. The following assumes that SRAM access is done through
CYNSE70064A device number 0.
Figure 12-10
and
Figure 12-11
show the timing diagram for device number 0 and device
number 7, respectively.
Cycle 1A
: The host ASIC applies the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the address
with DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the
DQ[25:21] lines. The host ASIC also supplies SADR[21:20] on CMD[8:7] in this cycle.
Note
. CMD[2] must be set to 0 for SRAM
Write, as burst Writes into the SRAM are not supported.
Cycle 1B
: The host ASIC continues to apply the Write instruction on the CMD[1:0] using CMDV = 1. The DQ bus supplies the
address with DQ[20:19] set to 10 to select the SRAM address.
Note
. CMD[2] must be set to 0 for SRAM Write, as burst Writes
into the SRAM are not supported.
Cycle 2
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
Cycle 3
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70064A.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation, but the Write cycle appears at the SRAM
bus with the same latency as that of a Search instruction as measured from the second cycle of the Write command.
SRAM Write with a Table of up to Eight Devices
cycle
1
CLK2X
CMDV
CMD[1:0]
DQ
Write
Address
ACK
OE_L
WE_L
ALE_L
SADR
Address
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1.
Figure 12-8. SRAM Write Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
PHS_L
CMD[8:2]
A
B
x
x
0
1
z
z
1
SSV
0
0
SSF
CE_L
1
x
1
0
0
0
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