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| 型號： | CYNSE70064A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Search Engine |
| 中文描述： | 搜索引擎 |
| 文件頁數(shù)： | 19/127頁 |
| 文件大?。?/td> | 3275K |
| 代理商： | CYNSE70064A |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 19 of 127
10.3
The Read can be a single Read of a data array, a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst
Read of the data (CMD[2] = 1) or mask array locations using an internal auto-incrementing address register (RBURADR).
A description of each type is provided in
Table 10-3
. A single-location Read operation lasts six cycles, as shown in
Figure 10-1
.
The burst Read adds two cycles for each successive Read. The SADR[21:20] bits supplied in the Read instruction cycle A drives
SADR[21:20] signals during the Read of an SRAM location.
Table 10-3. Read Command Parameters
CMD Parameter CMD[2]
Read Command
0
Single Read
Reads a single location of the data array, mask array, external SRAM, or
device registers. All access information is applied on the DQ bus.
1
Burst Read
Reads a block of locations from the data array, or mask array as a burst.
The internal register (RBURADR) specifies the starting address and the
length of the data transfer from the data or mask array, and it auto-incre-
ments the address for each access. All other access information is
applied on the DQ bus.
Note
. The device registers and external SRAM
can only be read in single-Read mode.
Read Command
The single Read operation takes six clock cycles, in the following sequence.
Cycle 1
: The host ASIC applies the Read instruction on the CMD[1:0] (CMD[2] = 0) using CMDV = 1 and the DQ bus supplies
the address, as shown in
Table 10-4
and
Table 10-5
. The host ASIC selects the CYNSE70064A for which ID[4:0] matches the
DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the CYNSE70064A with the LDEV bit set. The host ASIC
also supplies SADR[21:20] on CMD[8:7] in cycle A of the Read instruction if the Read is directed to the external SRAM.
Cycle 2
: The host ASIC floats DQ[67:0] to three-state condition.
Note:
5.
The 272-bit-configured devices or 272-bit-configured quadrants within devices do not support the Learn instruction.
Search
A
SADR[21]
SADR[20]
x
GMR Index 2:0]
68-bit or 136-bit: 0
272-bit:
1 in first cycle
0 in second cycle
1
0
B
A
B
SSRI[2:0]
SADR[20]
0
Comparand Register Index
Comparand Register Index
Comparand Register Index
1
1
1
0
1
1
Learn
[5]
SADR[21]
0
x
Mode
0: 68-bit
1: 136-bit
Description
Table 10-2. Command Parameters
(continued)
CMD
CYC
8
7
6
5
4
3
2
1
0
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
Read
Address
FF
Data
CLK2X
CMDV
CMD[1:0]
ACK
DQ
CMD[8:2]
A
B
PHS_L
Figure 10-1. Single-Location Read Cycle Timing
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相關(guān)代理商/技術(shù)參數(shù) |
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| CYNSE70064A-66BG | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70064A-66BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70064A-83BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Network Processing |
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