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| 型號(hào)： | CYNSE70064A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Search Engine |
| 中文描述： | 搜索引擎 |
| 文件頁數(shù)： | 25/127頁 |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 25 of 127
Note
. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B. The even
and odd pair of GMRs selected for the compare must be programmed with the same value.
The logical 68-bit Search operation is shown in
Figure 10-7
. The entire table consisting of 68-bit entries is compared to a 68-bit
word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective
GMR is the 68-bit word specified by the identical value in both even and odd GMR pairs selected by the GMR Index in the
command’s cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the command) is also stored in both
even and odd comparand register pairs selected by the Comparand Register Index in the command’s cycle B. In a ×68 configu-
ration, only the even comparand register can be subsequently used by the Learn command. The word K (presented on the DQ
bus in both cycles A and B of the command) is compared with each entry in the table starting at location 0. The first matching
entry’s location address L is the winning address that is driven as part of the SRAM address on the SADR[21:0] lines (See “SRAM
Addressing” on page 100.).
67
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (two CLK2X cycles) is shown in
Table 10-10
.
Table 10-10. The Latency of Search from Instruction to SRAM Access Cycle
Number of Devices
Max Table Size
1 (TLSZ = 00)
32K × 68 bits
1–8 (TLSZ = 01)
256K × 68 bits
1–31 (TLSZ = 10)
992K × 68 bits
The latency of a Search from command to SRAM access cycle is 4 for a single device in the table and TLSZ = 00. In addition,
SSV and SSF shift further to the right for different values of HLAT, as specified in
Table 10-11
.
Table 10-11. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
10.7
The hardware diagram of the Search subsystem of eight devices is shown in
Figure 10-8
. The following are the parameters
programmed into the eight devices.
First seven devices (devices 0–6): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0.
Eighth device (device 7): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1.
68-bit Search on Tables Configured as ×68 Using up to Eight CYNSE70064A Devices
Latency in CLK Cycles
4
5
6
Number of CLK Cycles
0
1
2
3
4
5
6
7
CFG = 00000000
(68-bit configuration)
67
0
Location
address
0
1
2
3
32767
K
GMR
Comparand Register (odd)
K
Comparand Register (even)
K
0
67
0
(First matching entry)
L
Figure 10-7. ×68 Table with One Device
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