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參數(shù)資料
| 型號： | CYNSE70064A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Search Engine |
| 中文描述： | 搜索引擎 |
| 文件頁數(shù)： | 10/127頁 |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 10 of 127
3.0
Product Summary
3.1
Logic Block Diagram
4.0
Functional Description
The following subsections contain command (CMD) and DQ bus (command and databus), database entry, arbitration logic,
pipeline and SRAM control, and full logic descriptions.
4.1
CMD[8:0] carries the CMD and its associated parameter. DQ[67:0] is used for data transfer to and from the database entries,
which comprise a data and a mask field that are organized as data and mask arrays. The DQ bus carries the Search data (of the
data and mask arrays and internal registers) during the Search command as well as the address and data during Read and/or
Write operations. The DQ bus can also carry the address information for the flow-through accesses to the external SRAMs and/or
SSRAMs.
CMD Bus and DQ Bus
4.2
Each database entry comprises a data and a mask field. The resultant value of the entry is “1,” “0,” or “X (don’t care),” depending
on the value in the data and mask bits. The on-chip priority encoder selects the first matching entry in the database that is nearest
to location 0.
Database Entry (Data Array and Mask Array)
4.3
When multiple search engines are cascaded to create large databases, the data being searched is presented to all search engines
simultaneously in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the search
engines will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the
SRAM bus.
Arbitration Logic
Compare/PIO Data
CMD
Configurable as
32K × 68
16K × 136
8K × 272
Data Array
A
M
DQ[67:0]
CMDV
ACK
EOT
CMD[8:0]
LHI[6:0]
Command
Decode
and PIO Access
P
Arbitration
Logic
LHO[1:0]
BHO[2:0]
SSF
SSV
Pipeline
and
SRAM
Control
SADR[21:0]
OE_L
WE_L
CE_L
ID[4:0]
BHI[2:0]
TAP
TAP
Controller
ALE_L
FULO[1:0]
FULI[6:0]
Full Logic
FULL
RST_L
PHS_L
CLK2X
Comparand Register Pairs [15:0]
Global Mask Register Pairs [7:0]
Information and Command Register
Burst Read Register
Burst Write Register
Next-Free Address Register
Search Successful Index Registers [7:0]
[All registers are 68 bits wide.]
Configurable as
32K × 68
16K × 136
8K × 272
Mask Array
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相關(guān)代理商/技術(shù)參數(shù) |
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| CYNSE70064A-50BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70064A-66BG | 制造商:Cypress Semiconductor 功能描述: |
| CYNSE70064A-66BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70064A-83BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Search Engine |
| CYNSE70128 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Network Processing |
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