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| 型號(hào)： | CYNSE70064A |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Search Engine |
| 中文描述： | 搜索引擎 |
| 文件頁(yè)數(shù)： | 18/127頁(yè) |
| 文件大小： | 3275K |
| 代理商： | CYNSE70064A |
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CYNSE70064A
Document #: 38-02041 Rev. *E
Page 18 of 127
9.0
Data and Mask Addressing
Figure 9-1
shows CYNSE70064A data and mask array addressing.
68
10.0
Commands
A master device such as an ASIC controller issues commands to the CYNSE70064A device using the command valid (CMDV)
signal and the CMD bus. The following subsections describe the operation of the commands.
10.1
The CYNSE70064A implements four basic commands, shown in
Table 10-1
. The command code must be presented to CMD[1:0]
while keeping the CMDV signal HIGH for two CLK2X cycles (designated as cycles A and B). The controller ASIC must align the
instructions using the PHS_L signal. The CMD[8:2] field passes the parameters of the command in cycles A and B.
Table 10-1. Command Codes
Command Code
Command
00
Read
Reads one of the following: data array, mask array, device registers, or external SRAM.
01
Write
Writes one of the following: data array, mask array, device registers, or external SRAM.
10
Search
Searches the data array for a desired pattern using the specified register from the GMR
array and local mask associated with each data cell.
11
Learn
The device has internal storage for up to 16 comparands that it can learn. The device
controller can insert these entries at the next-free address (as specified by the NFA
register) using the Learn instruction.
Command Codes
10.2
Table 10-2
lists the CMD bus fields that contain the CYNSE70064A command parameters and their respective cycles. Each
command is described separately in the subsections that follow.
Table 10-2. Command Parameters
Commands and Command Parameters
Description
CMD
Read
CYC
A
8
7
6
x
5
0
4
0
3
0
2
1
0
0
0
SADR[21]
SADR[20]
0 = Single
1 = Burst
0 = Single
1 = Burst
0 = Single
1 = Burst
0 = Single
1 = Burst
B
0
0
0
0
0
0
0
0
Write
A
SADR[21]
SADR[20]
x
GMR Index [2:0]
0
1
B
0
0
0
GMR Index [2:0]
0
1
CFG = 00000000
(68-bit configuration)
CFG = 10101010
(272-bit configuration)
67
0
0
1
2
3
32767
283
0
68
68
3
7
2
6
1
5
0
4
32764
32765
32766
32767
68
68
CFG = 01010101
(136-bit configuration)
135
0
68
68
1
3
5
7
0
2
4
6
32766
32767
32K
8K
64K
Figure 9-1. Addressing of the CYNSE70064A Data and Mask Arrays
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