
Coprocessor Interface
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
7-3
7.1.2
External coprocessors
Coprocessors determine the instructions that they must execute by using a
pipeline
follower
in the coprocessor. As each instruction arrives from memory, it enters both the
ARM pipeline and the coprocessor pipeline. To avoid a critical path for the instruction
being latched by the coprocessor, the coprocessor pipeline must operate one clock phase
behind the ARM940T pipeline. The ARM940T then informs the coprocessor when
instructions move from Decode into Execute, and if the instruction has to be executed.
To enable coprocessors to continue execution of coprocessor data operations while the
ARM940T pipeline is stalled (for example, waiting for a cache linefill to occur), the
coprocessor must monitor a clock
CPCLK
, and a clock stall signal
nCPWAIT
. If
nCPWAIT
is LOW on the rising edge of
CPCLK
, the ARM940T pipeline is stalled
and the coprocessor pipeline must not advance.
Figure 7-1 on page 7-3 indicates the timing for these signals and when the coprocessor
pipeline can advance its state. In this diagram, Coproc clock shows the result of ORing
CPCLK
with the inverse of
nCPWAIT
. This is one technique for generating a clock
that reflects the ARM940T pipeline advancing.
Figure 7-1 ARM940T coprocessor clocking
Coprocessor instructions
There are three classes of coprocessor instructions:
LDC or STC
Load from coprocessor register to memory and store to
coprocessor register from memory.
MCR or MRC
Register transfer between coprocessor and ARM processor core.
CDP
Coprocessor data operation.
Advance
Stall
Advance
CPCLK
nCPWAIT
Coproc
clock
Coprocessor
pipeline