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參數(shù)資料
| 型號(hào)： | ARM940T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | TECHNICAL REFERENCE MANUAL |
| 中文描述： | 技術(shù)參考手冊(cè) |
| 文件頁(yè)數(shù)： | 100/230頁(yè) |
| 文件大?。?/td> | 1144K |
| 代理商： | ARM940T |
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Coprocessor Interface
7-6
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
In this example, four words of data are transferred. The number of words transferred is
determined by how the coprocessor drives the
CHSDE[1:0]
and
CHSEX[1:0]
buses.
As with all other instructions, the ARM940T processor core performs the main
instruction decode off the rising edge of the clock during the Decode stage. From this,
the core commits to executing the instruction, and so performs an instruction fetch. The
coprocessor instruction pipeline must keep in step with the ARM940T by monitoring
nCPMREQ
, a latched copy of the ARM940T instruction memory request signal
InMREQ
. Whenever
nCPMREQ
is LOW, an instruction fetch is occurring and
CPID
is updated with the fetched instruction in the next cycle. This means that the instruction
currently on
CPID
must enter the Decode stage of the coprocessor pipeline, and that the
instruction in the Decode stage of the coprocessor pipeline must enter its Execute stage.
During the Execute stage, the condition codes are combined with the flags to determine
if the instruction must be executed or not. The output
CPPASS
is asserted (HIGH) if
the instruction in the Execute stage of the coprocessor pipeline:
is a coprocessor instruction
has passed its condition codes.
If a coprocessor instruction busy-waits,
CPPASS
is asserted on every cycle until the
coprocessor instruction is executed. If an interrupt occurs during busy-waiting,
CPPASS
is driven LOW, and the coprocessor must stop execution of the coprocessor
instruction.
An additional output,
CPLATECANCEL
, is used to cancel a coprocessor instruction
when the instruction preceding it caused a Data Abort. This is valid on the rising edge
of
CPCLK
on the cycle after the first Execute cycle of the coprocessor instructions.
CPLATECANCEL
is only asserted during the first Memory cycle of a coprocessor
instruction execution.
On the falling edge of the clock, the ARM940T processor core examines the
coprocessor handshake signals
CHSDE[1:0]
or
CHSEX[1:0]
:
if a new instruction is entering the Execute stage in the next cycle, it examines
CHSDE[1:0]
if the coprocessor instruction currently in Execute requires another Execute cycle,
it examines
CHSEX[1:0]
.
The handshake signals encode one of four states:
ABSENT
If there is no coprocessor attached that can execute the coprocessor
instruction, the handshake signals indicate the ABSENT state. In this
case, the ARM940T processor core takes the undefined instruction
exception.
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