
Bus Interface Unit
6-16
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
When a
SWP
instruction is executed on the ARM940T, the behavior is dependent on the
memory region being accessed, and it is up to the programmer to ensure correct
operation.
Typically for multi-master operations, the
SWP
instruction is used for passing
semaphores between the masters. For this type of operation, the semaphore must be
stored in an NCNB or NCB region of memory. When a
SWP
instruction is executed, any
cache linefills complete and the write buffer drains before the
SWP
instruction memory
accesses take place. During the
SWP
access, the
BLOK
signal goes HIGH to indicate that
the two memory accesses are indivisible.
For
SWP
instructions that access an NCB region of memory, any cache linefills complete,
and the write buffer drains before the read takes place. During the read,
BLOK
is driven
HIGH. The write operation then takes place as an unbuffered write. This is to allow
external aborts to be taken.
When a
SWP
instruction accesses a cachable region of memory, the access is protected as
a normal data access. The
BLOK
signal remains LOW throughout this operation.
If a region of memory is changed from being cachable to noncachable and the cache is
not flushed, it is possible for a cache hit to occur for the read access of the
SWP
instruction. This is a programming error that must be avoided.
6.2.10
AMBA ASB slave transfers
You can test the ARM940T as an individual module within an AMBA system,
responding only to transfers from the AMBA ASB. In this mode of operation the
ARM940T is never granted the ASB as a bus master, and responds as an ASB slave,
detecting the assertion of
DSEL
. This is described in detail in the
AMBA Specification
(REV 2.0)
.