
Debug Support
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
8-13
8.5.1
Reset
The JTAG interface includes a state-machine controller (the TAP controller). To force
the TAP controller into the correct state after power-up of the device, a reset pulse must
be applied to the
nTRST
signal. If the JTAG interface is to be used,
nTRST
must be
driven LOW, and then HIGH again. If the boundary scan interface is not to be used, the
nTRST
input can be tied permanently LOW.
Note
A clock on
TCK
is not necessary to reset the device.
The action of reset is as follows:
1.
System mode is selected. The boundary scan chain cells do not intercept any of
the signals passing between the external system and the core.
2.
The IDCODE instruction is selected. If the TAP controller is put into the Shift-DR
state and
TCK
is pulsed, the contents of the ID register are clocked out of
TDO
.
8.5.2
Pull-up resistors
The IEEE 1149.1 standard effectively requires
TDI
and
TMS
to have internal pull-up
resistors. To minimize static current draw, these resistors are not fitted to the ARM940T.
Accordingly, the four inputs to the test interface (the
TDO
,
TDI
, and
TMS
signals plus
TCK
) must all be driven to valid logic levels to achieve normal circuit operation.
8.5.3
Instruction register
The instruction register is four bits in length. There is no parity bit. The fixed value
loaded into the instruction register during the CAPTURE-IR controller state is 0001.
8.5.4
Public instructions
Table 8-1 on page 8-13 shows the public instructions that are supported.
Table 8-1 Public instructions
Instruction
Binary code
EXTEST
0000
SCAN_N
0010
INTEST
1100