xvi
List of Tables
AMD-K6
-
III
Processor Data Sheet
21918B/0—October 1999
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Valid Masks and Range Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 215
SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
I/O Trap Dword Configuration . . . . . . . . . . . . . . . . . . . . . . . . .220
I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Boundary Scan Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . .229
Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . .230
Supported Tap Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Tag versus Data Selector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
DR7 LEN and RW Definitions . . . . . . . . . . . . . . . . . . . . . . . . .246
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Typical and Maximum Power Dissipation . . . . . . . . . . . . . . . . 262
CLK Switching Characteristics for 100-MHz Bus Operation . 268
CLK Switching Characteristics for 66-MHz Bus Operation . . 268
Output Delay Timings for 100-MHz Bus Operation . . . . . . . . 270
Input Setup and Hold Timings for 100-MHz Bus Operation . 272
Output Delay Timings for 66-MHz Bus Operation . . . . . . . . . 274
Input Setup and Hold Timings for 66-MHz Bus Operation . . 276
RESET and Configuration Signals for 100-MHz
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
RESET and Configuration Signals for 66-MHz
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 280
Test Signal Timing at 25 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . 280
Package Thermal Specification . . . . . . . . . . . . . . . . . . . . . . . . 285
321-Pin Staggered CPGA Package Specification . . . . . . . . . . 297
Valid Ordering Part Number Combinations . . . . . . . . . . . . . .299
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.