參數(shù)資料
型號： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁數(shù)： 26/219頁
文件大?。?/td> 1065K
代理商： AM79C970A
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AMD
P R E L I M I N A R Y
26
Am79C970A
Expansion ROM Interface
ERA[7:0]
Expansion ROM Address
These pins provide the address to the Expansion ROM.
When
EROE
is asserted and ERACLK is driven HIGH,
ERA[7:0] contain the upper 8 bits of the Expansion ROM
address. They must be latched externally. When
EROE
is asserted and ERACLK is low, ERA[7:0] contain the
lower 8 bits of the Expansion ROM address.
Output
All ERA outputs are forced to a constant level to con-
serve power while no access to the Expansion ROM
is performed.
ERACLK
Expansion ROM Address Clock
When
EROE
is asserted and ERACLK is driven HIGH,
ERA[7:0] contain the upper 8 bits of the Expansion
ROM address. ERACLK is used to latch the address
bits externally. Both ’373 (transparent latch) and ’374
(D flip-flop) types of address latch are supported.
Output
ERD[7:0]
Expansion ROM Data
Data from the Expansion ROM is transferred on
ERD[7:0]. When
EROE
is high, the ERD[7:0] inputs are
internally disabled and can be left floating.
Input
Note that the ERD[7:0] pins are multiplexed with the
GPSI interface.
EROE
Expansion ROM Output Enable
This signal is asserted when the Expansion ROM
is read.
Output
Attachment Unit Interface
CI
±
Collision In
CI
±
is a differential input pair signaling the PCnet-PCI II
controller that a collision has been detected on the net-
work media, indicated by the CI
±
inputs being driven
with a 10 MHz pattern of sufficient amplitude and pulse
width to meet ISO 8802-3 (IEEE/ANSI 802.3) stan-
dards. Operates at pseudo ECL levels.
Input
DI
±
Data In
DI
±
is a differential input pair to the PCnet-PCI II control-
ler carrying Manchester encoded data from the network.
Operates at pseudo ECL levels.
Input
DO
±
Data Out
DO
±
is a differential output pair from the PCnet-PCI II
controller for transmitting Manchester encoded data to
the network. Operates at pseudo ECL levels.
Output
DXCVR
Disable Transceiver
The DXCVR signal is provided to power down an exter-
nal transceiver or DC-to-DC converter in designs that
provide more than one network connection.
Output
The polarity of the asserted state of the DXCVR output is
controlled by DXCVRPOL (BCR2, bit 4). By default, the
DXCVR output is high when asserted. When the
10BASE-T interface is the active network port, the
DXCVR output is always deasserted. When the AUI or
GPSI interface is the active network port, the assertion
of the DXCVR output is controlled by the setting of
DXCVRCTL (BCR2, bit 5).
Note that the DXCVR pin is multiplexed with the
NOUT pin.
Twisted Pair Interface
LNKST
Link Status
This output is designed to directly drive an LED. By de-
fault,
LNKST
indicates an active link connection on the
10BASE-T interface. This pin can also be programmed
to indicate other network status (see BCR4). The
LNKST
pin polarity is programmable, but by default, it is
active LOW.
Output
Note that the
LNKST
pin is multiplexed with the
EEDI pin.
RXD
±
10BASE-T Receive Data
10BASE-T port differential receivers.
Input
TXD
±
10BASE-T Transmit Data
10BASE-T port differential drivers.
Output
TXP
±
10BASE-T Pre-Distortion Control
These outputs provide transmit pre-distortion control in
conjunction with the 10BASE-T port differential drivers.
Output
General Purpose Serial Interface
CLSN
Collision
CLSN is an input, indicating that a collision has occurred
on the network.
Input
Note that the CLSN pin is multiplexed with the ERD3 pin.
RXCLK
Receive Clock
RXCLK is an input. Rising edges of the RXCLK signal
are used to sample the data on the RXDAT input when-
ever the RXEN input is HIGH.
Input
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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