參數(shù)資料
型號(hào)： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁(yè)數(shù)： 143/219頁(yè)
文件大小： 1065K
代理商： AM79C970A
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P R E L I M I N A R Y
AMD
143
Am79C970A
Table 31. DXCVR Output Control
Active
DXCVR
Output
DXCVRCTL
DXCVRPOL
Network Port
X
0
10BASE-T
Low
X
1
10BASE-T
High
0
0
AUI or GPSI
Low
1
0
AUI or GPSI
High
0
1
AUI or GPSI
High
1
1
AUI or GPSI
Low
Read/Write accessible always.
DXCVRPOL
is
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
cleared
by
3
EADISEL
EADI Select. When set to ONE,
this bit enables the three EADI in-
terface pins that are multiplexed
with other functions. EESK/
LED1
becomes SFBD, EEDO/
LED3
becomes SRD, and
LED2
be-
comes SRDCLK.
Read/Write accessible always.
EADISEL
is
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
cleared
by
2
AWAKE
This bit selects one of two differ-
ent sleep modes.
If AWAKE is set to ONE and the
SLEEP
pin is asserted, the
PCnet-PCI II controller goes into
snooze mode. If AWAKE is
cleared to ZERO and the
SLEEP
pin is asserted, the PCnet-PCI II
controller goes into coma mode.
See the section “Power Saving
Modes” for more details.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/Write accessible always.
AWAKE is cleared to ZERO by
H_RESET and is unaffected by
S_RESET or by setting the
STOP bit.
1
ASEL
Auto Select. When set, the
PCnet-PCI II controller will auto-
matically select the operating
media interface port, unless the
user has selected GPSI mode
through appropriate program-
ming of the PORTSEL bits of the
Mode Register (CSR15). If GPSI
mode has not been selected,
ASEL has been set to ONE, and
the 10BASE-T transceiver is in
the
Link
Pass
10BASE-T port will be used. If
GPSI mode has not been se-
lected, ASEL has been set to
ONE, and the 10BASE-T port is
in the Link Fail state, the AUI port
will be used. If one of the above
conditions changes during trans-
mission, switching between the
ports will not occur until the trans-
mission is ended.
state,
the
When ASEL is set to ONE, Link
Beat Pulses will be transmitted
on the 10BASE-T port, regard-
less of the state of Link Status.
When ASEL is cleared to ZERO,
Link Beat Pulses will only be
transmitted on the 10BASE-T
port when the PORTSEL bits of
the Mode Register (CSR15)
have selected 10BASE-T as the
active port.
When ASEL is cleared to ZERO,
then the selected network port
will be determined by the settings
of the PORTSEL bits of CSR15.
Read/Write accessible always.
ASEL is set to ONE by H_RESET
and is unaffected by S_RESET
or by setting the STOP bit.
The network port configurations
are as follows:
Table 32. Network Port Configuration
ASEL
Link Status
(of 10BASE-T)
Network
Port
PORTSEL[1:0] (BCR2[1])
0X
1
Fail
AUI
0X
1
Pass
10BASE-T
00
0
X
AUI
01
0
X
10BASE-T
10
X
X
GPSI
11
X
X
Reserved
0
XMAUSEL
Reserved location. Read/Write
accessible always. This reserved
location is cleared by H_RESET
and is unaffected by S_RESET
or by setting the STOP bit. Writ-
ing a ONE to this bit has no effect
on
the
operation
PCnet-PCI II controller.
of
the
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