參數(shù)資料
型號(hào)： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁(yè)數(shù)： 150/219頁(yè)
文件大小： 1065K
代理商： AM79C970A
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AMD
P R E L I M I N A R Y
150
Am79C970A
within the first 4
μ
s after every
transmission for the purpose of
SQE testing will not cause the
LEDOUT bit to be set.
Read/Write accessible always.
COLE is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
BCR7: LED3 Status
Bit
Name
Description
BCR7 determines which func-
tion(s) activate the
LED3
pin. The
pin will indicate the logical OR of
the enabled functions. BCR7
defaults to Transmit Status
(XMT) with pulse stretcher
enabled (PSE = 1).
Note that bits 15–0 in this register
are programmable through the
external EEPROM. Reserved
bits and read-only bits should be
programmed to ZERO.
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15
LEDOUT
This bit indicates the current
(non-stretched) value of the LED
output pin. A value of ONE in this
bit indicates that the OR of the
enabled signals is true.
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of this register (bits 8
and 6–0).
Read accessible always. This bit
is read only. Writes have no ef-
fect. LEDOUT is unaffected by
H_RESET, S_RESET or by set-
ting the STOP bit.
14
LEDPOL
LED Polarity. When this bit has
the value ZERO, the LED pin will
be asserted LOW whenever the
OR of the enabled signals is true,
and the LED pin will be disabled
and allowed to float whenever
the OR of the enabled signals is
false. (The LED output will be an
open drain output, and the output
value will be the inverse of the
LEDOUT status bit.)
When this bit has the value ONE,
the LED pin will be asserted
HIGH whenever the OR of the
enabled signals is true, and the
LED pin will be driven to a LOW
level whenever the OR of the
enabled signals is false. (The
LED output will be a totem pole
output, and the output value will
be the same polarity as the
LEDOUT status bit.)
The setting of this bit will not ef-
fect the polarity of the LEDOUT
bit for this register.
Read/Write accessible always.
LEDPOL is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
13
LEDDIS
LED Disable. This bit is used to
disable the LED output. When
LEDDIS is set to ONE and
LEDPOL is cleared to ZERO, the
LED output pin will be floating.
When LEDDIS is set to ONE and
LEDPOL is set to ONE, the LED
output pin will be driven LOW.
When LEDDIS has the value
ZERO, the LED output value will
be governed by the LEDOUT and
LEDPOL values.
Read/Write accessible always.
LEDDIS is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
12–10
RES
Reserved locations. Written as
ZEROs and read as undefined.
Magic Packet Status Enable.
When this bit is set to ONE, a
value of ONE is passed to the
LEDOUT bit in this register when
magic packet mode is enabled
and a magic packet is detected
on the network.
Read/Write accessible always.
MPSE is cleared by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
Full-duplex Link Status Enable.
Indicates the full-duplex Link
Test Status. When this bit is set
to ONE, a value of ONE is
passed to the LEDOUT signal
when the PCnet-PCI II controller
is functioning in a Link Pass state
and full-duplex operation is en-
abled. When the PCnet-PCI II
controller is not functioning in a
Link Pass state with full-duplex
operation being enabled, a value
of ZERO is passed to the
LEDOUT signal.
9
MPSE
8
FDLSE
When the 10BASE-T port is ac-
tive, a value of ONE is passed to
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