參數(shù)資料
型號(hào)： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁(yè)數(shù)： 217/219頁(yè)
文件大?。?/td> 1065K
代理商： AM79C970A
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AMD
E-3
Am79C970A
I
New bit: MPMODE (bit 1), Magic Packet Mode.
Was reserved location, read and written as ZERO.
I
New bit: SPND (bit 0), Suspend. Was reserved
location, read and written as ZERO.
CSR15: Mode
I
PORTSEL (bits 8–7), Network Port Select. New
option, value of 10b selects GPSI mode.
CSR58: Software Style
I
New bit: APERREN (bit 10), Advanced Parity Error
Handling Enable. Was reserved location, read and
written as ZERO.
I
SWSTYLE (bits 7–0), Software Style. New option,
value of THREE selects new PCnet-PCI controller
style that reorders 32-bit descriptor entries to allow
burst accesses.
CSR80: DMA Transfer Counter and FIFO
Threshold Control
I
RCVFW (bits 13–12), Receive FIFO Watermark.
Decoding adjusted for the larger FIFO size.
I
XMTSP (bits 11–10), Transmit Start Point. Decod-
ing adjusted for the larger FIFO size.
I
XMTFW (bits 9–8), Transmit FIFO Watermark. De-
coding adjusted for the larger FIFO size.
I
DMATC (bits 7–0), DMA Transfer Count.
Function of the counter is optimized for the PCI
bus environment.
CSR82: Bus Activity Timer
I
DMABAT (bits 15–0), DMA Bus Activity Timer.
Function of the counter is optimized for the PCI
bus environment.
CSR88: Chip ID Lower
I
New value: 1003h. Was 0003h.
CSR89: Chip ID Upper
I
New value : 0262h. Was 0243h.
CSR100: Bus Timeout
I
Default value now 0600h (153.6
μ
s) to adjust to
the larger FIFO size. Default value was 0200h
(51.2
μ
s).
CSR112: Missed Frame Count
I
Counter is stopped while the device is in
suspend mode
Bus Configuration Registers
BCR2: Miscellaneous Configuration
I
New bit: INTLEVEL (bit 7), Interrupt Level. Was
reserved location, read and written as ZERO.
I
New bit: DXCVRCTL (bit 5), DXCVR Control. Was
reserved location, read and written as ZERO.
I
New bit: DXCVRPOL (bit 4), DXCVR Polarity. Was
reserved location, read and written as ZERO.
I
New bit: EADISEL (bit 3), EADI Select. Was re-
served location, read and written as ZERO.
BCR4: Link Status LED
I
Register is now programmable through
the EEPROM
I
New bit: MPSE (bit 9), Magic Packet Status En-
able. Was reserved location, read and written
as
ZERO.
I
New bit: FDLSE (bit 8), Full Duplex Link Status
Enable. Was reserved location, read and written as
ZERO.
I
COLE (bit 0), Collision Status Enable. Corrected
behavior of function. LED will not light up due to
SQE test collision signal.
BCR5: LED1 Status
I
Register is now programmable through the
EEPROM
I
New bit: MPSE (bit 9), Magic Packet Status En-
able. Was reserved location, read and written as
ZERO.
I
New bit: FDLSE (bit 8), Full Duplex Link Status
Enable. Was reserved location, read and written as
ZERO.
I
COLE (bit 0), Collision Status Enable. Corrected
behavior of function. LED will not light up due to
SQE test collision signal.
BCR6: LED2 Status
I
New register. Was reserved location, the settings
of the register have no effect on the operation of
the device.
BCR7: LED3 Status
I
Register is now programmable through
the EEPROM
I
New bit: MPSE (bit 9), Magic Packet Status En-
able. Was reserved location, read and written as
ZERO.
I
New bit: FDLSE (bit 8), Full Duplex Link Status
Enable. Was reserved location, read and written as
ZERO.
I
COLE (bit 0), Collision Status Enable. Corrected
behavior of function. LED will not light up due to
SQE test collision signal.
BCR9: Full Duplex Control
I
New register. Was reserved location, read and
written as ZERO.
BCR16: I/O Base Address Lower
I
This register is no longer programmable through
the EEPROM. The register is reserved and has no
effect on the operation of the device. It is only used
in the PCnet-32.
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