參數(shù)資料
型號： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁數(shù)： 123/219頁
文件大?。?/td> 1065K
代理商： AM79C970A
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P R E L I M I N A R Y
AMD
123
Am79C970A
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
CSR9: Logical Address Filter 1
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Logical
Address
LADRF[31:16]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on
this register.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0LADRF[31:16]
Filter,
only
CSR10: Logical Address Filter 2
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Logical
Address
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on
this register.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0LADRF[47:32]
Filter,
only
CSR11: Logical Address Filter 3
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Logical
Address
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on
this register.
15–0LADRF[63:48]
Filter,
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
accessible
only
CSR12: Physical Address Register 0
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Physical
Address
PADR[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0PADR[15:0]
Register,
only
CSR13: Physical Address Register 1
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Physical
Address
PADR[31:16]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write
accessible
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
15–0PADR[31:16]
Register,
only
CSR14: Physical Address Register 2
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Physical
Address
PADR[47:32]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
15–0PADR[47:32]
Register,
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
AM79C970AKC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C970AKCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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