參數(shù)資料
型號： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁數(shù)： 108/219頁
文件大?。?/td> 1065K
代理商： AM79C970A
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AMD
P R E L I M I N A R Y
108
Am79C970A
address so that the device does
not claim cycles not intended
for it.
MEMEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
I/O Space access enable. The
PCnet-PCI II controller will ignore
all I/O accesses when IOEN is
cleared. The host must set IOEN
before the first I/O access to the
device. The PCI I/O Base
Address
register
programmed with a valid I/O ad-
dress before setting IOEN.
IOEN is cleared by H_RESET
and is not effected by S_RESET
or by setting the STOP bit.
0
IOEN
must
be
PCI Status Register (Offset 06h)
The PCI Status register is a 16-bit register that contains
status information for the PCI bus related events. It is lo-
cated at offset 06h in the PCI Configuration Space.
Bit
Name
Description
15
PERR
Parity Error. PERR is set when
the PCnet-PCI II controller de-
tects a parity error.
The PCnet-PCI II controller sam-
ples the AD[31:0], C/
BE
[3:0] and
the PAR lines for a parity error at
the following times:
In slave mode, during the
address phase of any PCI
bus command.
In slave mode, for all I/O, mem-
ory and configuration write
commands
that
PCnet-PCI II controller when
data is transferred (
TRDY
and
IRDY
are asserted).
In master mode, during the
data phase of all memory
read commands.
In master mode, during the data
phase of the memory write com-
mand, the PCnet-PCI II controller
sets the PERR bit if the target re-
ports a data parity error by as-
serting the
PERR
signal.
PERR is not effected by the state
of the Parity Error Response en-
able bit (PCI Command register,
bit 6).
PERR is set by the PCnet-PCI II
controller and cleared by writing
a ONE. Writing a ZERO has no
effect. PERR is cleared by
H_RESET and is not affected by
select
the
S_RESET or by setting the
STOP bit.
Signaled SERR. SERR is set
when the PCnet-PCI II controller
detects an address parity error,
and both SERREN and PERREN
(PCI Command register, bits 8
and 6) are set.
SERR is set by the PCnet-PCI II
controller and cleared by writing
a ONE. Writing a ZERO has no
effect. SERR is cleared by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
Received
Master
RMABORT is set when the
PCnet-PCI II controller termi-
nates a master cycle with a mas-
ter abort sequence.
RMABORT
is
PCnet-PCI II controller and
cleared by writing a ONE. Writing
a
ZERO
has
RMABORT
is
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
Received
Target
RTABORT is set when a target
terminates a PCnet-PCI II con-
troller master cycle with a target
abort sequence.
RTABORT
is
PCnet-PCI II controller and
cleared by writing a ONE. Writing
a
ZERO
has
RTABORT
is
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
Send Target Abort. Read as
ZERO, write operations have
no effect. The PCnet-PCI II con-
troller will never terminate a
slave access with a target
abort sequence.
STABORT is read only.
Device Select timing. DEVSEL is
set to 01b (medium), which
means that the PCnet-PCI II
controller will assert
DEVSEL
two clock periods after
FRAME
is asserted.
DEVSEL is read only.
Data Parity Error detected.
DATAPERR is set when the
PCnet-PCI II controller is the cur-
rent bus master and it detects a
14
SERR
13
RMABORT
Abort.
set
by
the
no
cleared
effect.
by
12
RTABORT
Abort.
set
by
the
no
cleared
effect.
by
11
STABORT
10–9 DEVSEL
8
DATAPERR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
AM79C970AKC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
AM79C970AKCW 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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