參數(shù)資料
型號(hào)： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁(yè)數(shù)： 131/219頁(yè)
文件大小： 1065K
代理商： AM79C970A
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P R E L I M I N A R Y
AMD
131
Am79C970A
CSR47: Polling Interval
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 POLLINT
Polling Interval. This register
contains the time that the
PCnet-PCI II controller will wait
between successive polling op-
erations. The POLLINT value is
expressed as the two’s comple-
ment of the desired interval,
where each bit of POLLINT rep-
resents
one
POLLINT[3:0] are ignored. The
sign of the two’s complement
POLLINT value is implied to be a
one, so POLLINT[15] does not
represent the sign bit, but is the
MSB of the number.
clock
period.
The default value of this register
is 0000h. This corresponds to a
polling interval of 65,536 clock
periods
(1.966
CLK = 33 MHz). The POLLINT
value of 0000h is created during
the microcode initialization rou-
tine, and therefore might not be
seen when reading CSR47 after
H_RESET or S_RESET.
ms
when
If the user desires to program a
value for POLLINT other than the
default, the correct procedure is
to first set only INIT in CSR0.
When the initialization sequence
is complete, the user must set
STOP (CSR0, bit 2) or SPND
(CSR5, bit 0). Then the user may
write to CSR47 and then set
STRT in CSR0. In this way, the
default value of 0000h in CSR47
will be overwritten with the de-
sired user value.
If the user does not use the stan-
dard
initialization
(standard implies use of an in-
itialization block in memory and
setting the INIT bit of CSR0), but
instead chooses to write directly
to each of the registers that are
involved in the INIT operation, it
is imperative that the user also
write to CSR47 as part of the al-
ternative initialization sequence.
procedure
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
accessible
only
S_RESET or by setting the
STOP bit.
CSR58: Software Style
Bit
Name
Description
This register is an alias of the lo-
cation BCR20. Accesses to/from
this register are equivalent to ac-
cesses to BCR20.
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–11
RES
Reserved locations. Written as
ZEROs and read as undefined.
10
APERREN
Advanced Parity Error Handling
Enable. When APERREN is set
to ONE, the BPE bits (RMD1 and
TMD1, bit 23) are used to
indicated parity error in data
transfers to the receive and
transmit buffers. Note that since
the advanced parity error han-
dling uses an additional bit in the
descriptor, SWSTYLE (bits 7–0
of this register) must be set to
ONE, TWO or THREE to pro-
gram the PCnet-PCI II controller
to use 32-bit software structures.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur
when the PCnet-PCI II controller
is the target of the transfer.
Read accessible always, write
accessible only when either
the STOP or the SPND bit is
set. APERREN is cleared by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
9
CSRPCNET
CSR PCnet-ISA configuration.
When set, this bit indicates that
the PCnet-PCI II controller regis-
ter bits of CSR4 and CSR3 will
map directly to the CSR4 and
CSR3 bits of the PCnet-ISA
(Am79C960)
device.
cleared, this bit indicates that
PCnet-PCI II controller register
bits of CSR4 and CSR3 will map
directly to the CSR4 and
CSR3
bits
of
(Am79C900) device.
When
the
ILACC
The value of CSRPCNET is
determined by the PCnet-PCI II
controller
according
setting of the Software Style
to
the
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