參數(shù)資料
型號(hào)： AM79C970A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
中文描述： PCnet - 2的PCI單芯片全雙工以太網(wǎng)控制器，適用于PCI總線產(chǎn)品
文件頁(yè)數(shù)： 124/219頁(yè)
文件大小： 1065K
代理商： AM79C970A
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AMD
P R E L I M I N A R Y
124
Am79C970A
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
accessible
only
CSR15: Mode
Bit
Name
Description
This register’s fields are loaded
during the PCnet-PCI II controller
initialization routine with the cor-
responding initialization block
values. The host can also write
directly to this register.
Reserved locations. Written as
ZEROs and read as undefined.
Promiscuous Mode.
When PROM is set to ONE,
all incoming receive frames
are accepted.
Read/Write
accessible
when either the STOP or the
SPND bit is set.
Disable
Receive
When set, this bit disables
the PCnet-PCI II controller from
receiving broadcast messages.
DRCVBC has no effect when
PROM is set to ONE.
Read/Write
accessible
when either the STOP or the
SPND bit is set. DRCVBC is
cleared
by
S_RESET and not affected
by STOP.
Disable Receive Physical Ad-
dress. When set, the physical ad-
dress detection (Station or node
ID) of the PCnet-PCI II controller
will be disabled. Frames ad-
dressed to the node’s individual
physical address will not be rec-
ognized. DRCVPA has no effect
when PROM is set to ONE.
31–16
RES
15
PROM
only
14
DRCVBC
Broadcast.
only
H_RESET
or
13
DRCVPA
Read/Write
when either the STOP or the
SPND bit is set.
Disable Link Status. When
DLNKTST is set to ONE, moni-
toring of Link Pulses is disabled.
When DLNKTST is cleared to
ZERO, monitoring of Link Pulses
is enabled. This bit only has
meaning when the 10BASE-T
network interface is selected.
Read/Write
accessible
when either the STOP or the
SPND bit is set.
Disable Automatic Polarity Cor-
rection. When DAPC is set to
ONE, the 10BASE-T receive po-
larity reversal algorithm is dis-
abled. When DAPC is cleared to
ZERO, the polarity reversal algo-
rithm is enabled.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/Write
accessible
when either the STOP or the
SPND bit is set.
MENDEC Loopback Mode. See
the description of the LOOP bit
in CSR15.
Read/Write
accessible
when either the STOP or the
SPND bit is set.
Low Receive Threshold (T-MAU
Mode only)
Transmit Mode Select (AUI
Mode only)
Low Receive Threshold. When
LRT is set to ONE, the internal
twisted pair receive thresholds
are reduced by 4.5 dB below
the standard 10BASE-T value
(approximately 3/5) and the
unsquelch threshold for the
RXD circuit will be 180 mV–
312 mV peak.
accessible
only
12
DLNKTST
only
11
DAPC
only
10
MENDECL
only
9
LRT
TSEL
LRT
Table 23. Network Port Configuration
ASEL
(BCR2[1])
Link Status
(of 10BASE-T)
PORTSEL[1:0]
Network Port
0X
1
Fail
AUI
0X
1
Pass
10BASE-T
00
0
X
AUI
01
0
X
10BASE-T
10
X
X
GPSI
11
X
X
Reserved
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