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參數(shù)資料
| 型號： | ADSP-2191 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數(shù)： | 7/52頁 |
| 文件大?。?/td> | 1873K |
| 代理商： | ADSP-2191 |
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–7–
REV. 0
ADSP-2191M
assigned a priority level of 11 are aliased to the lowest priority bit
position (15) in these registers and share vector address
0x00 01E0.
Interrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
emulation, power-down, and reset interrupts are nonmaskable
with the IMASK register, but software can use the DIS INT
instruction to mask the power-down interrupt.
The Interrupt Control (ICNTL) register controls interrupt
nesting and enables or disables interrupts globally.
The general-purpose Programmable Flag (PFx) pins can be con-
figured as outputs, can implement software interrupts, and (as
inputs) can implement hardware interrupts. Programmable Flag
pin interrupts can be configured for level-sensitive, single
edge-sensitive, or dual edge-sensitive operation.
The IRPTL register is used to force and clear interrupts. On-chip
stacks preserve the processor status and are automatically main-
tained during interrupt handling. To support interrupt, loop, and
subroutine nesting, the PC stack is 33 levels deep, the loop stack
is eight levels deep, and the status stack is 16 levels deep. To
prevent stack overflow, the PC stack can generate a stack-level
interrupt if the PC stack falls below three locations full or rises
above 28 locations full.
The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.
ENA INT;
DIS INT;
At reset, interrupt servicing is disabled.
For quick servicing of interrupts, a secondary set of DAG and
computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the DSP’s state.
DMA Controller
The ADSP-2191M has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-2191M’s internal memory and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-capa-
ble peripherals include the Host port, SPORTs, SPI ports, and
UART. Each individual DMA-capable peripheral has a dedicated
DMA channel. To describe each DMA sequence, the DMA con-
troller uses a set of parameters—called a DMA descriptor. When
successive DMA sequences are needed, these DMA descriptors
can be linked or chained together, so the completion of one DMA
sequence auto-initiates and starts the next sequence. DMA
sequences do not contend for bus access with the DSP core;
instead DMAs “steal” cycles to access memory.
Table 1. Interrupt Priorities/Addresses
Interrupt
Emulator (NMI)—
Highest Priority
Reset (NMI)
Power-Down (NMI)
Loop and PC Stack
Emulation Kernel
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt
User Assigned Interrupt—
Lowest Priority
IMASK/
IRPTL
NA
Vector
Address
1
NA
1
These interrupt vectors start at address 0x10000 when the DSP is in
“no-boot,” run from external memory mode.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0x00 0000
0x00 0020
0x00 0040
0x00 0060
0x00 0080
0x00 00A0
0x00 00C0
0x00 00E0
0x00 0100
0x00 0120
0x00 0140
0x00 0160
0x00 0180
0x00 01A0
0x00 01C0
0x00 01E0
Table 2. Peripheral Interrupts and Priority at Reset
Interrupt
ID
Reset
Priority
Slave DMA/Host Port Interface
SPORT0 Receive
SPORT0 Transmit
SPORT1 Receive
SPORT1 Transmit
SPORT2 Receive/SPI0
SPORT2 Transmit/SPI1
UART Receive
UART Transmit
Timer 0
Timer 1
Timer 2
Programmable Flag A (any PFx)
Programmable Flag B (any PFx)
Memory DMA port
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
10
11
11
11
11
Table 3. Interrupt Control (ICNTL) Register Bits
Bit
0–3
4
5
6
7
8–9
10
11
12–15
Description
Reserved
Interrupt Nesting Enable
Global Interrupt Enable
Reserved
MAC-Biased Rounding Enable
Reserved
PC Stack Interrupt Enable
Loop Stack Interrupt Enable
Reserved
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| ADSP-2191MBCA-140 | 功能描述:IC DSP CONTROLLER 16BIT 144MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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