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參數(shù)資料
| 型號： | ADSP-2191 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數(shù)： | 41/52頁 |
| 文件大小： | 1873K |
| 代理商： | ADSP-2191 |
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–41–
REV. 0
ADSP-2191M
Output Drive Currents
Figure 25
shows typical I-V characteristics for the output drivers
of the ADSP-2191M. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Number of output pins that switch during each cycle (O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (V
DD
)
and is calculated by the formula below.
The load capacitance includes the processor’s package capaci-
tance (C
IN
). The switching frequency includes driving the load
high and then back low. Address and data pins can drive high and
low at a maximum rate of 1/(2t
CK
). The write strobe can switch
every cycle at a frequency of 1/t
CK
. Select pins switch at 1/(2t
CK
),
but selects can switch on each cycle. For example, estimate P
EXT
with the following assumptions:
A system with one bank of external data memory—asyn-
chronous RAM (16-bit)
One 64K 16 RAM chip is used with a load of 10 pF
Maximum peripheral speed CCLK = 80 MHz, HCLK =
80 MHz
External data memory writes occur every other cycle, a
rate of 1/(4t
HCLK
), with 50% of the pins switching
The bus cycle time is 80 MHz (t
HCLK
= 12.5 nsec)
The P
EXT
equation is calculated for each class of pins that can
drive as shown in
Table 23
.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.
Where:
P
EXT
is from
Table 23
P
INT
is I
DDINT
2.5 V, using the calculation I
DDINT
listed in
Power Dissipation on page 41
.
Note that the conditions causing a worst-case P
EXT
are different
from those causing a worst-case P
INT
. Maximum P
INT
cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by – V is dependent on the capacitive load, C
L
and the
load current, I
L
. This decay time can be approximated by the
equation below.
Figure 25. Typical Drive Currents
SOURCE (
VDDEXT
) VOLTAGE – V
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
S
D
)
–100
–80
–60
–40
–20
0
20
40
60
4.0
V
DDEXT
= 3.65V @
– 40°C
V
DDEXT
= 3.3V @
+ 25°C
V
OH
V
DDEXT
= 3.0V @
+ 85°C
V
OL
V
DDEXT
= 3.0V @
+ 85°C
V
DDEXT
= 3.3V @
+ 25°C
V
DDEXT
= 3.65V @
– 40°C
INPUT CURRENT
OUTPUT CURRENT
P
EXT
O
C
×
V
DD
2
×
f
×
=
Table 23. P
EXT
Calculation Example
Pin Type
Address
MSx
WR
Data
CLKOUT
# of Pins
15
1
1
16
1
% Switching
50
0
—
50
—
C
f
20 MHz
20 MHz
40 MHz
20 MHz
80 MHz
V
DD
2
10.9 V
10.9 V
10.9 V
10.9 V
10.9 V
= P
EXT
= .01635 W
= 0 W
= .00436 W
= .01744 W
= .00872 W
P
EXT
=.04687 W
10 pF
10 pF
10 pF
10 pF
10 pF
P
TOTAL
P
=
EXT
P
INT
+
t
DECAY
C
V
I
L
---------------
=
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