參數(shù)資料
型號: ADSP-2191
廠商: Analog Devices, Inc.
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: DSP微機
文件頁數(shù): 5/52頁
文件大?。?/td> 1873K
代理商: ADSP-2191
–5–
REV. 0
ADSP-2191M
Three programmable interval timers generate periodic inter-
rupts. Each timer can be independently set to operate in one of
three modes:
Pulse Waveform Generation mode
Pulsewidth Count/Capture mode
External Event Watchdog mode
Each timer has one bidirectional pin and four registers that
implement its mode of operation: A 7-bit configuration register,
a 32-bit count register, a 32-bit period register, and a 32-bit
pulsewidth register. A single status register supports all three
timers. A bit in each timer’s configuration register enables or
disables the corresponding timer independently of the others.
Memory Architecture
The ADSP-2191M DSP provides 64K words of on-chip SRAM
memory. This memory is divided into four 16K blocks located
on memory Page 0 in the DSP’s memory map. In addition to the
internal and external memory space, the ADSP-2191M can
address two additional and separate off-chip memory spaces: I/O
space and boot space.
As shown in
Figure 2
, the DSP’s two internal memory blocks
populate all of Page 0. The entire DSP memory map consists of
256 pages (Pages 0
255), and each page is 64K words long.
External memory space consists of four memory banks (banks
0–3) and supports a wide variety of SRAM memory devices. Each
bank is selectable using the memory select pins (
MS3–0
) and has
configurable page boundaries, waitstates, and waitstate modes.
The 1K word of on-chip boot-ROM populates the top of
Page 255 while the remaining 254 pages are addressable off-chip.
I/O memory pages differ from external memory pages in that I/O
pages are 1K word long, and the external I/O pages have their
own select pin (
IOMS
). Pages 0–7 of I/O memory space reside
on-chip and contain the configuration registers for the peripher-
als. Both the core and DMA-capable peripherals can access the
DSP’s entire memory map.
Internal (On-Chip) Memory
The ADSP-2191M’s unified program and data memory space
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA and DMA buses. The DSP uses slightly
Figure 2. Memory Map
BANK3
(MS3)
BANK2
(MS2)
BANK1
(MS1)
BANK0
(MS0)
BLOCK0, 24-BIT
BLOCK2, 16-BIT
BLOCK1, 24-BIT
BLOCK3, 16-BIT
RESERVED
BOOT ROM, 24-BIT
0 00 4000
0 00 8000
0 01 0000
0 40 0000
0 80 0000
0 C0 0000
0 FF 0000
0 FF 0400
0 FF 03FF
0 FF FFFF
LOGICAL
ADDRESS
64K WORD
MEMORY
PAGES
PAGE 0
PAGES 1–63
PAGES 64–127
PAGES 128–191
PAGES 192–254
PAGE 255
INTERNAL
MEMORY
EXTERNAL
MEMORY
(16- BIT)
INTERNAL
MEMORY
MEMORY SELECTS
(MS)
FOR PORTIONS OF THE
MEMORY MAP APPEAR
WITH THE SELECTED
MEMORY.
PAGES 1–254
0 01 0000
0 FE FFFF
I/O MEMORY
16- BIT
1K WORD
PAGES 8–255
1K WORD
PAGES 0–7
LOWER PAGE BOUNDARIES
ARE CONFIGURABLE FOR
BANKS OF EXTERNAL MEMORY.
BOUNDARIES SHOWN ARE
BANK SIZES AT RESET.
0 07 3FF
0 00 000
0 08 000
0 FF 3FF
INTERNAL
EXTERNAL
(IOMS)
0 00 0000
0 00 C000
8-BIT 10-BIT
BOOT MEMORY
16-BIT
(BMS)
64K WORD
LOGICAL
ADDRESS
LOGICAL
ADDRESS
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