參數(shù)資料
型號: ADSP-2192
廠商: Analog Devices, Inc.
元件分類: 數(shù)字信號處理
英文描述: DSP Microcomputer
中文描述: DSP微機(jī)
文件頁數(shù): 1/40頁
文件大?。?/td> 1307K
代理商: ADSP-2192
a
DSP Microcomputer
ADSP-2192M
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
REV. 0
ADSP-2192M DUAL CORE DSP FEATURES
320 MIPS ADSP-219x DSP in a 144-Lead LQFP Package
with PCI, USB, Sub-ISA, and CardBus Interfaces
3.3 V/5.0 V PCI 2.2 Compliant 33 MHz/32-bit Interface
with Bus Mastering over Four DMA Channels with
Scatter-Gather Support
Integrated USB 1.1 Compliant Interface
Sub-ISA Interface
AC’97 Revision 2.1 Compliant Interface for External
Audio, Modem, and Handset Codecs with DMA
Capability
Dual ADSP-219x Core Processors (P0 and P1) on Each
ADSP-2192M DSP Chip
132K Words of Memory Includes 4K
16-Bit Shared
Data Memory
80K Words of On-Chip RAM on P0, Configured as
64K Words On-Chip 16-Bit RAM for Data Memory and
16K Words On-Chip 24-Bit RAM for Program Memory
48K Words of On-Chip RAM on P1, Configured as
32K Words On-Chip 16-Bit RAM for Data Memory and
16K Words On-Chip 24-Bit RAM for Program Memory
4K Words of Additional On-Chip RAM Shared by Both
Cores, Configured as 4K Words On-Chip 16-Bit RAM
Flexible Power Management with Selectable Power-
Down and Idle Modes
Programmable PLL Supports Frequency Multiplication,
Enabling Full Speed Operation from Low Speed
Input Clocks
2.5 V Internal Operation Supports 3.3 V/5.0 V
Compliant I/O
FUNCTIONAL BLOCK DIAGRAM
PROCESSOR P0
CORE
INTERFACE
ADSP-219x
DSP CORE
(SEE FIGURE 1
ON PAGE 3)
SHARED
MEMORY
4K 16 DM
P0
MEMORY
16K 24 PM
64K 16 DM
BOOT ROM
ADDR DATA
P1
MEMORY
16K 24 PM
32K 16 DM
BOOT ROM
ADDR DATA
P0 DMA
CONTROLLER
FIFOS
SHARED DSP
I/O MAPPED
REGISTERS
P1 DMA
CONTROLLER
FIFOS
HOST PORT
PCI 2.2
OR
USB 1.1
GP I/O PINS
(AND
OPTIONAL
SERIAL
EEPROM)
JTAG
EMULATION
PORT
ADDR DATA
ADDR DATA
ADDR DATA
ADDR DATA
SERIAL PORT
AC'97
COMPLIANT
PROCESSOR P1
CORE
INTERFACE
ADSP-219
x
DSP CORE
(SEE FIGURE 1
ON PAGE 3)
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
Fax:781/326-8703
www.analog.com
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