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參數(shù)資料
| 型號： | ADSP-2192 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機(jī) |
| 文件頁數(shù)： | 23/40頁 |
| 文件大?。?/td> | 1307K |
| 代理商： | ADSP-2192 |
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–23–
REV. 0
ADSP-2192M
FIFO Control Registers
The Transmit FIFO Control Register has the following bit field
definitions:
CE (Bits 1–0): Connection Enable (00 = Disable,
01 = Reserved, 10 = Connect to AC’97, and
11 = Reserved)
DPSel (Bit 2): Reserved (0)
SMSel (Bit 3): Stereo/Mono Select - AC’97 Mode Only
(0 = Mono Stream or 1 = Stereo Stream)
SLOT (Bits 7–4): AC’97 Slot Select - AC’97 Mode Only
FIP (Bits 10–8): FIFO interrupt position. An interrupt is
generated when FIP[2:0] words remain in the FIFO. The
interrupt is level-sensitive.
DME (Bit 11): DMA Enable. (0 = DMA Disabled or
1 = DMA Enabled)
TFF (Bit 13): Transmit FIFO Full - Read Only.
(0 = FIFO Not Full or 1 = FIFO Full)
TFE (Bit 4): Transmit FIFO Empty - Read Only.
(0 = FIFO Not Empty or 1 = FIFO Empty)
TU (Bit 15): Transmit Underflow – Sticky, Write 1 Clear.
(0 = FIFO Underflow has not occurred or 1 = FIFO
Underflow has occurred)
The Receive FIFO Control Register has the following bit field
definitions:
CE (Bits 1–0): Connection Enable. (00 = Disable,
01 = Reserved, 10 = Connect to AC’97, 11 = Reserved)
DPSel (Bit 2): Reserved (0)
SMSel (Bit 3): Stereo/Mono Select - AC’97 Mode Only.
(0 = Mono Stream or 1 = Stereo Stream)
SLOT (Bits 7–4): AC’97 Slot Select - AC’97 Mode Only.
FIP (Bit 10–8): FIFO interrupt position. An interrupt is
generated when FIP[2:0] + 1 words have been received
in the FIFO. The interrupt is level-sensitive.
DME (Bit 11): DMA Enable. (0 = DMA Disabled or
1 = DMA Enabled)
RFF (Bit 13): Receive FIFO Full – Read Only. (0 = FIFO
Not Full or 1 = FIFO Full)
RFE (Bit 14): Receive FIFO Empty – Read Only.
(0 = FIFO Not Empty or 1 = FIFO Empty)
RO (Bit 15): Receive Overflow – Sticky, Write 1 Clear.
(0 = FIFO Overflow has not occurred or 1 = FIFO
Overflow has occurred)
System Reset Description
There are several sources of reset to the ADSP-2192M.
Power-On Reset
PCI Reset
USB Reset
Soft Reset (
RST
in CMSR Register)
Power-On Reset
The DSP has an internal power-on reset circuit that resets the
DSP when power is applied. The DSP also has a Power-On Reset
PORST
signal that can initiate this master reset. Note that
PORST
is not needed when using PCI or USB (and is shown as
a no connect in
Figure 7
); these interfaces reset the DSP under
their control as needed.
DSP Software Reset
The DSP can generate a software reset using the RSTD bit in
DSP Interrupt/Power-down Registers). Generally, reset condi-
tions are handled by forcing the DSPs to execute ROM- or
RAM-based Reset Handler code. The Reset Handler that is
executed can be dictated by the Reset Source as defined by the
CRST[1:0] bits in the Chip Mode/Status Register (CMSR). The
exact Reset Functionality is therefore defined by the ROM and
RAM Reset Handler Code and as such is programmable.
Booting Modes
The ADSP-2192M has two mechanisms for automatically
loading internal program memory after reset. The CRST pins,
sampled during power-on reset, implement these modes:
Boot from PCI Host
Boot from USB Host
Table 25. AC’97 Slot Select Values
Slot
0000–0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101–1111
Mono
Reserved
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9
Slot 10
Slot 11
Slot 12
Reserved
Stereo
Reserved
Slots 3/4
Slots 4/5
Slots 5/6
Slots 6/7
Slots 7/8
Slots 8/9
Slots 9/10
Slots 10/11
Slots 11/12
Not Allowed
Reserved
Table 26. AC’97 Slot Select Values
Slot
Mono
Stereo
0000–0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101–1111
Reserved
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9
Slot 10
Slot 11
Slot 12
Reserved
Reserved
Slots 3/4
Slots 4/5
Slots 5/6
Slots 6/7
Slots 7/8
Slots 8/9
Slots 9/10
Slots 10/11
Slots 11/12
Not Allowed
Reserved
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