參數(shù)資料
型號(hào)： ADSP-2192
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁數(shù)： 28/40頁
文件大?。?/td> 1307K
代理商： ADSP-2192
ADSP-2192M
–28–
REV. 0
Additional Information
This data sheet provides a general overview of the ADSP-2192M
architecture and functionality. For detailed information on the
ADSP-219x Family core architecture and instruction set, refer
to the ADSP-219x
/2191 DSP Hardware Reference
.
PIN DESCRIPTIONS
ADSP-2192M pin definitions are listed in a series of tables
following this section. Inputs identified as synchronous (S) must
meet timing requirements with respect to CLKIN (or with
respect to TCK for TMS, TDI). Inputs identified as asynchro-
nous (A) can be asserted asynchronously to CLKIN (or to TCK
for
TRST
).
The following symbols appear in the Type columns of these
tables: G = Ground, I = Input, O = Output, P = Power Supply,
and T = Three-State.
Table 27. Pin Configurations:
PCI/USB Bus Interface
Pin Name
LQFP
I/O
Description
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0
57
56
55
54
53
48
47
46
44
43
42
37
36
35
34
33
15
14
13
12
11
8
7
6
3
2
143
142
141
138
137
136
45
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
Addr/Data Bus
PCI Cmd/Byte
Enable
PCI Cmd/Byte
Enable
CBE1
32
I/O
CBE2
16
I/O
PCI Cmd/Byte
Enable
PCI Cmd/Byte
Enable
PCI Clock
Clock Run
PCI Target Select
PCI Frame Select
Grant
PCI Initiator Select
PCI/ISA Interrupt
PCI Initiator Ready
PCI Bus Parity
PCI Ground
CBE3
4
I/O
CLK
CLKRUN
DEVSEL
FRAME
GNT
IDSEL
INTAB
IRDY
PAR
PCIGND
130
26
24
17
131
5
128
22
31
1, 10,
21, 30,
39, 52,
133
9, 18,
29, 38,
51,
132,
144
27
I
O
I/O
I/O
I
I
O
I/O
I/O
I
PCIVDD
I
PCI VDD supply
PERR
I/O
PCI Parity Error/
USB– (Inverting
Input)
PCI Power
Management Event
Request
PCI Reset
PCI System Error/
USB+ (Noninverting
Input)
PCI Target Stop
PCI Target Ready
PME
135
O
REQ
RST
SERR
134
129
28
O
I
O
STOP
TRDY
25
23
I/O
I/O
Table 28. Pin Configurations: Analog Pins
Pin Name
LQFP
I/O
Description
AGND
AQGND
CTRLAUX
CTRLVDD
IVDD
NC
NC
NC
RVAUX
RVDD
67
68
61
63
62
66
69
70
60
64
I
I
I
I
I
O
I
I
I
I
Analog Gnd.
Ref. Analog Gnd.
X Supply
Control VDD
Digital VDD
No Connect
No Connect
No Connect
X Supply
Analog VDD Supply
Table 27. Pin Configurations:
PCI/USB Bus Interface (continued)
Pin Name
LQFP
I/O
Description
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