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參數(shù)資料
| 型號： | ADSP-2192 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 1307K |
| 代理商： | ADSP-2192 |
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REV. 0
ADSP-2192M
CardBus PC Cards generate less heat and consume less power.
This is attained by:
Low voltage operation at 3.3 V
Software control of clock speed
Advanced power management mechanism
AC’97 2.1 External Codec Interface
The industry standard AC’97 serial interface (AC-Link) incor-
porates a 7-pin digital serial interface that links compliant codecs
to the ADSP-2192M. The ACLink implements a bidirectional,
fixed rate, serial PCM digital stream. It handles multiple input
and output audio streams as well as control and status register
accesses using a time division multiplex scheme.
Serial EEPROM Interface
The Serial EEPROM for the ADSP-2192M can overwrite the
following information which is returned during the USB GET
DEVICE DESCRIPTOR command. During the Serial
EEPROM initialization procedure, the DSP is responsible for
writing the USB Descriptor Vendor ID, USB Descriptor Product
ID, USB Descriptor Release Number, and USB Descriptor
Device Attributes registers to change the default settings.
All descriptors can be changed when downloading the RAM-
based MCU renumeration code, except for the Manufacturer
and Product, which are supported in the CONFIG DEVICE and
cannot be overwritten or changed by the Serial EEPROM.
Vendor ID (0x0456)
Product ID (0x2192)
Device Release Number (0x0100)
Device Attributes (0x80FA): SP (1 = self-powered,
0 = bus-powered, default = 0); RW (1 = have remote
wake-up capability, 0 = no remote wake-up capability,
default = 0); C[7:0] (power consumption from bus
expressed in 2 mA units; default = 0xFA 500 mA)
Manufacturer (ADI)
Product (ADI Device)
Internal Interfaces
The ADSP-2192M provides three types of internal interfaces:
registers, codec, and DSP memory buses. The following sections
discuss those interfaces.
Register Interface
The register interface allows the PCI interface, USB interface,
and both DSPs to communicate with the I/O Registers. These
registers map into DSP, PCI, and USB I/O spaces.
Register Spaces
Several different register spaces are defined on the ADSP-
2192M, as described in the following sections.
PCI Configuration Space
These registers control the configuration of the PCI Interface.
Most of these registers are only accessible via the PCI Bus
although a subset is accessible to the DSP for configuration
during the boot.
DSP Core Register Space
Each DSP has an internal register that is accessible with no
latency. These registers are accessible only from within the DSP,
using the REG( ) instruction.
Peripheral Device Control Register Space
This Register Space is accessible by both DSPs, the PCI, Sub-
ISA, and USB Buses. Note that certain sections of this space are
exclusive to either the PCI, USB, or Sub-ISA Buses. These
registers control the operation of the peripherals of the ADSP-
2192M. The DSP accesses these registers using the I/O space
instruction.
USB Register Space
These registers control the operation and configuration of the
USB Interface. Most of these registers are only accessible via the
USB Bus, although a subset is accessible to the DSP.
CardBus Interface
The ADSP-2192M’s PC CardBus interface meets the state and
timing specifications defined for PCMCIA’s PC CardBus
Standard April 1998 Release 6.1. It supports up to three card
functions. Multiple function PC cards require a separate set of
Configuration registers per function. A primary Card Informa-
tion Structure common to all functions is required. Separate
secondary Card Information Structures, one per function, are
also required. Data for each CIS is loaded by the DSP during
bootstrap loading.
The host PC can read the CIS data at any time. If needed, the
WAIT control can be activated to extend the read operation to
meet bus write access to the CIS data.
Using the PCI Interface
The ADSP-2192M includes a 33 MHz, 32-bit PCI interface to
provide control and data paths between the part and the host
CPU. The PCI interface is compliant with the PCI Local Bus
Specification Revision 2.2. The interface supports bus mastering
as well as bus target interfaces. The PCI Bus Power Management
Interface Specification Revision 1.1 is supported and additional
features as needed by PCI designs are included.
Target/Slave Interface
The ADSP-2192M PCI interface contains three separate func-
tions, each with its own configuration space. Each function
contains four base address registers used to access ADSP-2192M
control registers and DSP memory. Base Address Register
(BAR) 1 is used to point to the control registers. The addresses
specified in these tables are offsets from BAR1 in each of the
functions. PCI memory-type accesses are used to read and write
the registers.
DSP memory accesses use BAR2 or BAR3 of each function.
BAR2 is used to access 24-bit DSP memory; BAR3 accesses
16-bit DSP memory. Maps of the BAR2 and BAR3 registers
appear in
Table 8 on Page 11
and
Table 9 on Page 12
.
The lower half of the allocated space pointed to by each DSP
memory BAR is the DSP memory for DSP core P0. The upper
half is the memory space associated with DSP core P1. PCI
transactions to and from DSP memory use the DMA function
within the DSP core. Thus each word transferred to or from PCI
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