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參數(shù)資料
| 型號： | ADSP-21992YST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Mixed Signal DSP Controller With CAN |
| 中文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 1/49頁 |
| 文件大?。?/td> | 602K |
| 代理商： | ADSP-21992YST |
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a
Preliminary Technical Data
Mixed Signal DSP Controller With CAN
This information applies to a product under development. Its characteristics and specifi-
cations are subject to change without notice. Analog Devices assumes no obligation
regarding future manufacturing unless otherwise agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
Fax:781/326-8703
www.analog.com
Analog Devices,Inc., 2002
REV. PrA
PRELIMINARY TECHNICAL DATA
ADSP-21992
MIXED SIGNAL DSP CONTROLLER FEATURES
ADSP-219x, 16-bit, Fixed Point DSP Core with up to 160
MIPS sustained performance
48K Words of On chip RAM, Configured as 32K Words
On chip 24-bit Program RAM and 16K Words On chip
16-bit Data RAM
External Memory Interface
Dedicated Memory DMA Controller for Data/Instruction
Transfer between Internal/External Memory
Programmable PLL and Flexible Clock Generation
Circuitry Enables Full speed Operation from Low
speed Input Clocks
IEEE JTAG Standard 1149.1 Test Access Port Supports
On chip Emulation and System Debugging
8-Channel, 20 MSPS, 14-bit Analog to Digital Converter
System
Three Phase 16-bit Center Based PWM Generation Unit
with 12.5 ns resolution
Dedicated 32-bit Encoder Interface Unit with
Companion Encoder Event Timer
Dual 16-bit Auxiliary PWM Outputs
16 General Purpose Flag I/O Pins
Three Programmable 32-bit Interval Timers
SPI Communications Port with Master or Slave
Operation
Synchronous Serial Communications Port (SPORT)
Capable of Software UART Emulation
Controller Area Network (CAN) Module Fully Compliant
with V2.0B Standard
FUNCTIONAL BLOCK DIAGRAM
ADC
CONTROL
VREF
PIPELINE
FLASH ADC
CLOCK
GENERATOR / PLL
PM ADDRESS/DATA
DM ADDRESS/DATA
I/O
16K X 16
DMRAM
(BLOCK 1)
32K X 24
PM RAM
(BLOCK 0)
EXTERNAL
MEMORY
INTERFACE
(EMI)
TIMER 0
TIMER 1
TIMER 2
4K X 24
PMROM
(BLOCK 2)
160 MHZ
ADSP-219X
DSP
JTAG
TEST &
EMULATION
ADDRESS
DATA
CONTROL
I/O REGISTERS
PWM
GENERATION
UNIT
ENCODER
INTERFACE
UNIT
(AND EET)
AUXILIARY
PWM
UNIT
FLAG
I/O
SPI
SPORT
WATCHDOG
TIMER
INTERRUPT
CONTROLLER
(ICNTL)
POR
MEMORY DMA
CONTROLLER
CONTROLLER
AREA
NETWORK
(CAN)
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