參數(shù)資料
型號(hào): ADSP-21992YST
廠商: ANALOG DEVICES INC
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: Mixed Signal DSP Controller With CAN
中文描述: 16-BIT, 100 MHz, OTHER DSP, PQFP176
封裝: LQFP-176
文件頁(yè)數(shù): 24/49頁(yè)
文件大?。?/td> 602K
代理商: ADSP-21992YST
PRELIMINARY TECHNICAL DATA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
24
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
Clock In and Clock Out Cycle Timing
Table 6
and
Figure 14
describe clock and reset operations. Per
V
DDINT
Internal (Core) Supply Voltage, –0.3 to 3.0 V on
page 23
, combinations of CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160/100 MHz.
Table 6. Clock In and Clock Out Cycle Timing
Parameter
Description
Min
Max
Unit
Switching Characteristic
t
CKOD
CLKOUT delay from CLKIN
0
5.8
ns
t
CKO
CLKOUT period
1
1
Figure 14
shows a 2 ratio between CLKOUT = 2
see the System Design chapter of the
ADSP-219x/2191 DSP Hardware Reference
.
2
In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN=CCLK), t
CK
=t
CCLK
.
3
In bypass mode, t
CK
=t
CCLK
.
CLKIN (or t
HCLK
= 2
t
CCLK
), but the ratio has many programmable options. For more information
10
ns
Timing Requirements
t
CK
CLKIN period
2,3
6.25
200
ns
t
CKL
CLKIN low pulse
2.2
ns
t
CKH
CLKIN high pulse
2.2
ns
t
WRST
RESET asserted pulsewidth low
200t
CLKOUT
ns
t
MSLS
MSELx/BYPASS stable before RESET de-asserted setup
450
μs
t
MSLH
MSELx/BYPASS stable after RESET de-asserted hold
10t
CLKOUT
ns
Figure 14. Clock In and Clock Out Cycle Timing
t
CKOD
CLKOUT
MSEL6–0
BYPASS
RESET
CLKIN
t
WRST
t
CKH
t
CK
t
CKL
t
MSLH
t
MSLS
t
CKO
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