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參數(shù)資料
| 型號： | ADSP-21992YST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Mixed Signal DSP Controller With CAN |
| 中文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 15/49頁 |
| 文件大?。?/td> | 602K |
| 代理商： | ADSP-21992YST |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
15
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
PRELIMINARY TECHNICAL DATA
Trace instruction execution
Profile program execution
Fill and dump memory
Source level debugging
Create custom debugger windows
The VisualDSP IDE lets programmers define and manage
DSP software development. Its dialog boxes and property
pages let programmers configure and manage all of the
ADSP-219x development tools, including the syntax high-
lighting in the VisualDSP editor. This capability permits:
Control how the development tools process inputs and
generate outputs.
Maintain a one-to-one correspondence with the tool’s
command line switches.
Analog Devices DSP emulators use the IEEE 1149.1 JTAG
test access port of the ADSP-21992 processor to monitor
and control the target board processor during emulation.
The emulator provides full-speed emulation, allowing
inspection and modification of memory, registers, and
processor stacks. Nonintrusive in-circuit emulation is
assured by the use of the processor’s JTAG interface—the
emulator does not affect target system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the ADSP-219x processor family.
Hardware tools include ADSP-219x PC plug-in cards.
Third Party software tools include DSP libraries, real-time
operating systems, and block diagram design tools.
Designing an Emulator Compatible DSP Board (Target)
The White Mountain DSP (Product Line of Analog
Devices, Inc.) family of emulators are tools that every DSP
developer needs to test and debug their hardware and
software system. Analog Devices has supplied an IEEE
1149.1 JTAG Test Access Port (TAP) on each JTAG DSP.
The emulator uses the TAP to access the internals of the
DSP, allowing the developer to load code, set breakpoints,
observe variables, observe memory, examine registers, etc.
The DSP must be halted to send data and commands, but
once an operation is completed by the emulator, the DSP
system is set running at full speed with no impact on system
timing.
To use these emulators, the target’s design must include the
interface between an Analog Devices JTAG DSP and the
emulation header on a custom DSP target board. The
following sections provide the guidelines for design that help
eliminate possible JTAG emulation port problems.
Target Board Connector
The emulator interface to an ADI JTAG DSP is a 14-pin
header, as shown in
Figure 6
. The customer must supply
this header on their target board in order to communicate
with the emulator. The interface consists of a standard dual
row 0.025" square post header, set on 0.1" x 0.1" spacing,
with a minimum post length of 0.235". Pin 3 is the key
position used to prevent the pod from being inserted back-
wards. This pin must be clipped on the target board.
Also, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least
0.15” and 0.10” around the length and width of the header,
and reserve a height clearance to attach and detach the pod
connector. For more information, see
Layout Require-
ments on page 17
.
As can be seen in
Figure 6
, there are two sets of signals on
the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO, TRST and , EMU used for emulation
purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and BTRST that are option-
ally used for board-level (boundary scan) testing. The "B"
signals would be connected to a separate on-board JTAG
boundary scan controller if used. Most customers will never
use the "B" signals. If they will not be used, tie all of them
to ground as shown in figure 2.
Note: BTCK can alternately be pulled up (for some older
silicon) to VDD (+5V, +3.3V, or +2.5V) using a 4.7K
resistor, as described in previous documents. Tying the
signal to ground is universal and will work for all silicon.
When the emulator is not connected to this header, place
jumpers across BTMS, BTCK, BTRST, and BTDI as
shown in
Figure 7
. This holds the JTAG signals in the
correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.
Figure 6. JTAG Target Board Connector for JTAG
Equiped Analog Devices DSP (Jumpers in
Place)
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
EMU
GND
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
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