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參數(shù)資料
| 型號： | ADSP-21992YST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Mixed Signal DSP Controller With CAN |
| 中文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 23/49頁 |
| 文件大?。?/td> | 602K |
| 代理商： | ADSP-21992YST |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
23
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
TIMING SPECIFICATIONS
This section contains timing information for the DSP’s
external signals.
2
Applies to output and bidirectional pins: DATA15–0, ADDR21–0, HAD15–0, MS3–0, IOMS, RD, WR, CLKOUT, HACK, PF7–0, TMR2–0, BGH,
BG, DT, DT1, DT2/MISO0, TCLK, TCLK1, TCLK2/SCK0, RCLK, RCLK1, RCLK2/SCK1, TFS, TFS1, TFS2/MOSI0, RFS, RFS1, RFS2/MOSI1,
BMS, TDO, TXD, EMU.
3
Applies to input pins: ACK, BR, HCMS, HCIOMS, BMODE2, BMODE1–0, HA16, HALE, HRD, HWR, CLKIN, RESET, TCK, TDI, TMS, TRST,
DR, DR1, BYPASS, RXD.
4
Applies to input pins with internal pull ups: TRST, BMODE0, BMODE1, BMODE2, BYPASS, TCK, TMS, TDI, RESET.
5
Applies to three statable pins: DATA15–0, ADDR21–0, MS3–0, RD, WR, PF7–0, BMS, IOMS, TFSx, RFSx, TDO, EMU.
6
The test program used to measure I
represents worst case processor operation and is not sustainable under normal application conditions. Actual
internal power measurements made using typical applications are less than specified.
For more information, see Power Dissipation on page 42.
7
Applies to all signal pins.
8
Guaranteed, but not tested.
V
DDINT
Internal (Core) Supply Voltage
1,2
. . . . . . –0.3 to 3.0 V
V
DDEXT
External (I/O) Supply Voltage . . . . . . . . –0.3 to 4.6 V
V
IL
–V
IH
Input Voltage . . . . . . . . . . . . . . . . . .–0.5 to +5.5 V
3
V
OL
–V
OH
Output Voltage Swing. . . . . . . . . . .–0.5 to +5.5 V
3
C
L
Load Capacitance. . . . . . . . . . . . . . . . . . . . . . . . 200 pF
t
CCLK
Core Clock Period . . . . . . . . . . . . . . . . . . . . . . 6.25 ns
f
CCLK
Core Clock Frequency . . . . . . . . . . . . . . . . . 160 MHz
t
HCLK
Peripheral Clock Period . . . . . . . . . . . . . . . . . . . .10 ns
f
HCLK
Peripheral Clock Frequency . . . . . . . . . . . . . . 80 MHz
T
STORE
Storage Temperature Range . . . . . . . . . .–65 to 150oC
T
LEAD
Lead Temperature (5 seconds) . . . . . . . . . . . . . 185oC
1
Specifications subject to change without notice.
2
Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
3
Except CLKIN and analog pins.
CAUTION:
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21992 features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.
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