參數(shù)資料
型號(hào)： ADSP-21992YST
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Mixed Signal DSP Controller With CAN
中文描述： 16-BIT, 100 MHz, OTHER DSP, PQFP176
封裝： LQFP-176
文件頁(yè)數(shù)： 42/49頁(yè)
文件大?。?/td> 602K
代理商： ADSP-21992YST
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
42
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
PRELIMINARY TECHNICAL DATA
Output Drive Currents
Figure 25
shows typical current and voltage characteristics
for the output drivers of the ADSP-21992. The curves
represent the current drive capability of the output drivers
as a function of output voltage.
Power Dissipation
Total power dissipation has two components, one due to
internal circuitry and one due to the switching of external
output drivers. Internal power dissipation is dependent on
the instruction execution sequence and the data operands
involved. Using the current specifications (I
DDINPEAK
, I
DDINHIGH
,
I
DDINLOW
, I
DDIDLE
) from the
Electrical Characteristics on
page 22
and the current versus operation information in
Table 17
, designers can estimate the ADSP-21992’s
internal power supply (V
DDINT
) input current for a specific
application, according to the formula in
Figure 26
.
The external component of total power dissipation is caused
by the switching of output pins. Its magnitude depends on:
The number of output pins that switch during each cycle
(O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (V
DD
)
and is calculated by the formula in
Figure 27
.
The load capacitance should include the processor’s
package capacitance (C
IN
). The switching frequency
includes driving the load high and then back low. Address
and data pins can drive high and low at a maximum rate of
1
(2t
CK
). The write strobe can switch every cycle at a
frequency of 1
t
CK
. Select pins switch at 1
(2t
CK
), but selects
can switch on each cycle. For example, estimate P
EXT
with
the following assumptions:
A system with one bank of external data memory—asyn-
chronous RAM (16-bit)
Four 8K 16 RAM chips are used, each with a load of 10
pF
External data memory writes occur every other cycle, a
rate of 1
(4t
CK
), with 50% of the pins switching
The bus cycle time is 50 MHz (t
CK
= 20 ns)
Figure 25. ADSP-21992 Typical Drive Currents
SOURCE (V
DDEXT
) VOLTAGE – V
–120
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
0
3.5
0.5
1
1.5
2.0
2.5
3.0
S
D
)
TBD
Table 17. ADSP-21992 Operation Types Versus Input Current
Operation
Instruction Type
Instruction Fetch
Core Memory Access
1
Internal Memory DMA
External Memory
DMA
Data bit pattern for core
memory access and
DMA
Typical Activity (I
DD TYPICAL
)
TBD
TBD
TBD
TBD
TBD
High Activity (I
DD IDLE
)
TBD
TBD
TBD
TBD
TBD
Low Activity (I
DD PWRDWN
)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1
These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
CK
and t
CCLK
), see
Clock Signals on page 13
.
Figure 26. I
DDINT
Calculation
I
DDINT
%Typical
I
DD-TYPICAL
×
(
)
=
%Idle
I
DD-IDLE
×
(
)
%Powerdown
I
DD-PWRDWN
×
(
)
+
+
Figure 27. P
EXT
Calculation
P
EXT
O
C
×
V
DD
2
×
f
×
=
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