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參數(shù)資料
| 型號： | ADSP-21992YST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Mixed Signal DSP Controller With CAN |
| 中文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 6/49頁 |
| 文件大?。?/td> | 602K |
| 代理商： | ADSP-21992YST |
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For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
6
REV. PrA
PRELIMINARY TECHNICAL DATA
erals can access the DSP’s off chip boot memory space. After
reset, the DSP always starts executing instructions from the
on chip boot ROM.
Bus Request and Bus Grant
The ADSP-21992 can relinquish control of the data and
address buses to an external device. When the external
device requires access to the bus, it asserts the bus request
(BR) signal. The (BR) signal is arbitrated with core and
peripheral requests. External Bus requests have the lowest
priority. If no other internal request is pending, the external
bus request will be granted. Due to synchronizer and arbi-
tration delays, bus grants will be provided with a minimum
of three peripheral clock delays. The ADSP-21992 will
respond to the bus grant by:
Three stating the data and address buses and the MS3–0,
BMS, IOMS, RD, and WR output drivers.
Asserting the bus grant (BG) signal.
The ADSP-21992 will halt program execution if the bus is
granted to an external device and an instruction fetch or
data read/write request is made to external general purpose
or peripheral memory spaces. If an instruction requires two
external memory read accesses, the bus will not be granted
between the two accesses. If an instruction requires an
external memory read and an external memory write access,
the bus may be granted between the two accesses. The
external memory interface can be configured so that the
core will have exclusive use of the interface. DMA and Bus
Requests will be granted. When the external device releases
BR, the DSP releases BG and continues program execution
from the point at which it stopped.
The bus request feature operates at all times, even while the
DSP is booting and RESET is active.
The ADSP-21992 asserts the BGH pin when it is ready to
start another external port access, but is held off because
the bus was previously granted. This mechanism can be
extended to define more complex arbitration protocols for
implementing more elaborate multimaster systems.
DMA Controller
The ADSP-21992 has a DMA controller that supports
automated data transfers with minimal overhead for the
DSP core. Cycle stealing DMA transfers can occur between
the ADSP-21992’s internal memory and any of its DMA
capable peripherals. Additionally, DMA transfers can be
accomplished between any of the DMA capable peripherals
and external devices connected to the external memory
interface. DMA capable peripherals include the SPORT
and SPI ports, and ADC Control module. Each individual
DMA capable peripheral has a dedicated DMA channel. To
describe each DMA sequence, the DMA controller uses a
set of parameters—called a DMA descriptor. When succes-
sive DMA sequences are needed, these DMA descriptors
can be linked or chained together, so the completion of one
DMA sequence auto initiates and starts the next sequence.
DMA sequences do not contend for bus access with the DSP
core, instead DMAs “steal” cycles to access memory.
All DMA transfers use the DMA bus shown in
Figure 1 on
page 3
. Because all of the peripherals use the same bus,
arbitration for DMA bus access is needed. The arbitration
for DMA bus access appears in
Table 1
.
DSP Peripherals Architecture
The ADSP-21992 contains a number of special purpose,
embedded control peripherals, which can be seen in the
Functional Block diagram on page 1. The ADSP-21992
contains a high performance, 8-channel, 14-bit ADC
system with dual channel simultaneous sampling ability
across 4 pairs of inputs. An internal precision voltage
reference is also available as part of the ADC system. In
addition, a three phase, 16-bit, center based PWM genera-
tion unit can be used to produce high accuracy PWM signals
with minimal processor overhead. The ADSP-21992 also
contains a flexible incremental encoder interface unit for
position sensor feedback; two adjustable frequency auxiliary
PWM outputs, 16 lines of digital I/O; a 16-bit watchdog
timer; three general purpose timers and an interrupt con-
troller that manages all peripheral interrupts. Finally, the
ADSP-21992 contains an integrated power-on-reset (POR)
circuit that can be used to generate the required reset signal
for the device on power-on.
The ADSP-21992 has an external memory interface that is
shared by the DSP’s core, the DMA controller, and DMA
capable peripherals, which include the ADC, SPORT, and
SPI communication ports. The external port consists of a
16-bit data bus, a 20-bit address bus, and control signals.
Figure 4. ADSP-21992 Boot Memory Map
PAGES 1 TO 254
64K WORDS/PAGE
0x01 0000
0xFE 0000
OFF-CHIP
BOOT MEMORY
16-BITS
Table 1. I/O Bus Arbitration Priority
DMA Bus Master
SPORT Receive DMA
SPORT Transmit DMA
ADC Control DMA
SPI0 Receive/Transmit DMA
Memory DMA
Arbitration Priority
0—Highest
1
2
3
4—Lowest
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