參數(shù)資料
型號： ADSP-21992YST
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Mixed Signal DSP Controller With CAN
中文描述： 16-BIT, 100 MHz, OTHER DSP, PQFP176
封裝： LQFP-176
文件頁數(shù)： 19/49頁
文件大小： 602K
代理商： ADSP-21992YST
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
19
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
PRELIMINARY TECHNICAL DATA
architecture, instruction set, communications ports and
embedded control peripherals, refer to the ADSP-21992
Mixed Signal DSP Controller Hardware Reference Manual
.
PIN DESCRIPTIONS
ADSP-21992 pin definitions are listed in
Table 5
. All
ADSP-21992 inputs are asynchronous and can be asserted
asynchronously to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to V
DDEXT
or GND,
except for ADDR21–0, DATA15–0, PF7-0, and inputs that
have internal pullup or pulldown resistors (TRST,
BMODE0, BMODE1, BMODE2, BYPASS, TCK, TMS,
TDI, PWMPOL, PWMSR, and RESET)—these pins can
be left floating. These pins have a logic level hold circuit that
prevents input from floating internally. PWMTRIP has an
internal pulldown, but should not be left floating to avoid
unnecessary PWM shutdowns.
The following symbols appear in the Type column of
Table 5
: G = Ground, I = Input, O = Output, P = Power
Supply, B = Bidirectional, T = Three State, D = Digital,
A = Analog, CKG = Clock Generation pin, PU = Internal
Pull Up, PD = Internal Pull Down, and OD = Open Drain.
Table 5. ADSP-21992 Pin Descriptions
Signal Name
A19 - A0
D15 - D0
RD
WR
ACK
BR
BG
BGH
MS0
MS1
MS2
MS3
IOMS
BMS
CLKIN
XTAL
CLKOUT
BYPASS
RESET
POR
BMODE2
BMODE1
BMODE0
TCK
TMS
TDI
TDO
TRST
EMU
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
ASHAN
BSHAN
Type
D, OT
D, BT
D, OT
D, OT
D, I
D, I, PU
D, O
D, O
D, OT
D, OT
D, OT
D, OT
D, OT
D, OT
D,I,CKG
D,O,CKG
D, OT
D, I, PU
D, I, PU
D, O
D, I, PU
D, I, PD
D, I, PU
D, I
D, I, PU
D, I, PU
D, OT
D, I, PU
D, OT, PU
A, I
A, I
A, I
A, I
A, I
A, I
A, I
A, I
A, I
A, I
Description
External Port Address Bus
External Port Data Bus
External Port Read Strobe
External Port Write Strobe
External Port Access Ready Acknowledge
External Port Bus Request
External Port Bus Grant
External Port Bus Grant Hang
External Port Memory Select Strobe 0
External Port Memory Select Strobe 1
External Port Memory Select Strobe 2
External Port Memory Select Strobe 3
External Port IO Space Select Strobe
External Port Boot Memory Select Strobe
Clock Input/Oscillator Input/ Crystal Connection 0
Oscillator Output/ Crystal Connection 1
Clock Output (HCLK)
PLL Bypass Mode Select
Processor Reset Input
Power on Reset Output
Boot Mode Select Input 2
Boot Mode Select Input 1
Boot Mode Select Input 0
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
JTAG Test Reset Input
Emulation Status
ADC Input 0
ADC Input 1
ADC Input 2
ADC Input 3
ADC Input 4
ADC Input 5
ADC Input 6
ADC Input 7
Inverting SHA_A Input
Inverting SHA_B Input
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