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參數(shù)資料
| 型號： | ADSP-21992YST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Mixed Signal DSP Controller With CAN |
| 中文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 44/49頁 |
| 文件大?。?/td> | 602K |
| 代理商： | ADSP-21992YST |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
44
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
PRELIMINARY TECHNICAL DATA
Output Enable Time
Output pins are considered to be enabled when they have
made a transition from a high impedance state to when they
start driving. The output enable time t
ENA
is the interval from
when a reference signal reaches a high or low voltage level
to when the output has reached a specified high or low trip
point, as shown in the Output Enable/Disable diagram
(
Figure 30
). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to
start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular
system, first calculate t
DECAY
using the equation given in
Figure 29
. Choose –V to be the difference between the
ADSP-21992’s output voltage and the input threshold for
the device requiring the hold time. A typical –V will be 0.4 V.
C
L
is the total bus capacitance (per data line), and I
L
is the
total leakage or three state current (per data line). The hold
time will be t
DECAY
plus the minimum disable time (i.e.,
t
DATRWH
for the write cycle).
Capacitive Loading
Output delays and holds are based on standard capacitive
loads: 50 pF on all pins (see
Figure 35
). The delay and hold
specifications given should be derated by a factor of
1.5 ns/50 pF for loads other than the nominal value of
50 pF.
Figure 33
and
Figure 34
show how output rise time
varies with capacitance. These figures also show graphically
how output delays and holds vary with load capacitance.
(Note that this graph or derating does not apply to output
disable delays; see
Output Disable Time on page 43
.) The
graphs in these figures may not be linear outside the ranges
shown.
Environmental Conditions
The thermal characteristics in which the DSP is operating
influence performance.
Thermal Characteristics
The ADSP-21992 comes in a 196-lead Ball Grid Array
(mini-BGA) package. The ADSP-21992 is specified for an
ambient temperature (T
AMB
) as calculated using the formula
in
Figure 36
. To ensure that the T
AMB
data sheet specification
is not exceeded, a heatsink and/or an air flow source may be
used. A heatsink should be attached to the ground plane (as
close as possible to the thermal pathways) with a thermal
adhesive.
Figure 33. Typical Output Rise Time (10%–90%,
V
DDEXT
=Max) vs. Load Capacitance
LOAD CAPACITANCE–PF
16.0
8.0
00
200
20
40
60
80
100
120
140
160
180
14.0
12.0
4.0
2.0
10.0
6.0
TBD
R
(
Figure 34. Typical Output Rise Time (10%-90%,
V
DDEXT
=Min) vs. Load Capacitance
Figure 35. Typical Output Delay or Hold vs. Load
Capacitance (at Max Case Temperature)
Figure 36. T
CASE
Calculation
3.5
0
3.0
2.5
2.0
1.5
1.0
0.5
LOAD CAPACITANCE–PF
0
200
20
40
60
80
100
120
140
160
180
TBD
R
(
LOAD CAPACITANCE–PF
5
–
25
50
75
100
125
150
175
4
3
2
1
TBD
O
NOMINAL
T
AMB
T
CASE
=
PD
θ
CA
×
–
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