參數(shù)資料
型號(hào)： ADSP-21992YST
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： Mixed Signal DSP Controller With CAN
中文描述： 16-BIT, 100 MHz, OTHER DSP, PQFP176
封裝： LQFP-176
文件頁(yè)數(shù)： 35/49頁(yè)
文件大?。?/td> 602K
代理商： ADSP-21992YST
PRELIMINARY TECHNICAL DATA
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
35
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
Serial Port (SPORT) Frame Synch Timing
Table 13
and
Figure 21
describe SPORT frame synch operations.
To determine whether communication is possible between two devices at clock speed n, the following specifications must
be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3)
R/TCLK width.
Table 13. Serial Port (SPORT) Frame Synch Timing
Parameter
Description
Min
Max
Unit
Switching Characteristics
t
HOFSE
RFS Hold after RCLK (Internally Generated RFS)
1
1
Referenced to drive edge.
2
MCE = 1, TFS enable and TFS valid follow t
DDTLFSE
and t
DDTENFS
.
3
Referenced to sample edge.
12.4
ns
t
HOFSI
TFS Hold after TCLK (Internally Generated TFS)
1
12.2
ns
t
DDTENFS
Data Enable from late FS or MCE = 1, MFD = 0
2
4.7
ns
t
DDTLFSE
Data Delay from Late External TFS or External RFS with
MCE = 1, MFD = 0
3
4.7
ns
t
HDTE
Transmit Data Hold after TCLK (external clk)
1
12.4
ns
t
HDTI
Transmit Data Hold after TCLK (internal clk)
1
0
12.2
ns
t
DDTE
Transmit Data Delay after TCLK (external clk)
1
0
12.2
ns
t
DDTI
Transmit Data Delay after TCLK (internal clk)
1
0
11.1
ns
Timing Requirements
t
SFSE
TFS/RFS Setup before TCLK/RCLK (external clk)
3
–0.6
TBD
ns
t
SFSI
TFS/RFS Setup before TCLK/RCLK (internal clk)
3
–0.6
TBD
ns
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