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參數(shù)資料
| 型號(hào)： | ADSP-21992YST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Mixed Signal DSP Controller With CAN |
| 中文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 8/49頁 |
| 文件大小： | 602K |
| 代理商： | ADSP-21992YST |
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For current information contact Analog Devices at (781) 937-1799
ADSP-21992
Clocking: the SPORT can use an external serial clock or
generate its own in a wide range of frequencies down to 0
Hz. Maximum clock value is 40 MHz for internally
generated clock.
Word length: each SPORT section supports serial data
word lengths from three to sixteen bits that can be trans-
ferred either MSB first or LSB first.
Framing: each SPORT section (receive and transmit) can
operate with or without frame synchronization signals for
each data word; with internally generated or externally
generated frame signals; with active high or active low
frame signals; with either of two pulse widths and frame
signal timing.
Companding in hardware: each SPORT section can
perform A law and μ law companding according to
CCITT recommendation G.711.
Direct Memory Access with single cycle overhead: using
the built in DMA master, the SPORT can automatically
receive and/or transmit multiple memory buffers of data
with an overhead of only one DSP cycle per data word.
The on chip DSP via a linked list of memory space
resident DMA descriptor blocks can configure transfers
between the SPORT and memory space. This chained list
can be dynamically allocated and updated.
Interrupts: each SPORT section (receive and transmit)
generates an interrupt upon completing a data word
transfer, or after transferring an entire buffer or buffers if
DMA is used.
Multi channel capability: The SPORT can receive and
transmit data selectively from channels of a serial bit
stream that is time division multiplexed into up to 128
channels. This is especially useful for T1 interfaces or as
a network communication scheme for multiple proces-
sors. The SPORTs also support T1 and E1 carrier
systems.
Each SPORT channel (TX and RX) supports a DMA
buffer of up to 8, 16-bit transfers.
The SPORT operates at a frequency of up to the clock
frequency of the HCLK
The SPORT is capable of UART software emulation.
August 2002
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
8
REV. PrA
PRELIMINARY TECHNICAL DATA
Controller Area Network (CAN) Module
The ADSP-21992 contains a Controller Area Network
(CAN) Module. Key features of the CAN Module are:
Conforms to the CAN V2.0B standard.
Supports both standard (11-bit) and extended (29-bit)
Identifiers
Supports Data Rates of up to 1Mbit/sec (and higher)
16 Configurable Mailboxes (All receive or transmit)
Dedicated Acceptance Mask for each Mailbox
Data Filtering (first 2 bytes) can be used for Acceptance
Filtering
Error Status and Warning registers
Transmit Priority by Identifier
Universal Counter Module
Readable Receive and Transmit Counters
The CAN Module is a low baud rate serial interface
intended for use in applications where baud rates are
typically under 1 Mbit/ sec. The CAN protocol incorporates
a data CRC check, message error tracking and fault node
confinement as means to improve network reliability to the
level required for control applications.
The CAN module architecture is based around a 16-entry
mailbox RAM. The mailbox is accessed sequentially by the
CAN serial interface or the host CPU. Each mailbox
consists of eight 16-bit data words. The data is divided into
fields, which includes a message identifier, a time stamp, a
byte count, up to 8 bytes of data, and several control bits.
Each node monitors the messages being passed on the
network. If the identifier in the transmitted message
matches an identifier in one of it's mailboxes, then the
module knows that the message was meant for it, passes the
data into it's appropriate mailbox, and signals the host of its
arrival with an interrupt.
The CAN network itself is a single, differential pair line. All
nodes continuously monitor this line. There is no clock wire.
Messages are passed in one of 4 standard message types or
frames. Synchronization is achieved by an elaborate sync
scheme performed in each CAN receiver. Message arbitra-
tion is accomplished 1 bit at a time. A dominant polarity is
established for the network. All nodes are allowed to start
transmitting at the same time following a frame sync pulse.
As each node transmits a bit, it checks to see if the bus is the
same state that it transmitted. If it is, it continues to
transmit. If not, then another node has transmitted a
dominant bit so the first node knows it has lost the arbitra-
tion and it stops transmitting. The arbitration continues, bit
by bit until only 1 node is left transmitting.
The electrical characteristics of each network connection
are very stringent so the CAN interface is typically divided
into 2 parts: a controller and a transceiver. This allows a
single controller to support different drivers and CAN
networks. The ADSP-21992 CAN module represents only
the controller part of the interface. This module's network
I/O is a single transmit line and a single receive line, which
communicate to a line transceiver.
Analog To Digital Conversion System
The ADSP-21992 contains a fast, high accuracy, multiple
input analog to digital conversion system with simultaneous
sampling capabilities. This A/D conversion system permits
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