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參數(shù)資料
| 型號： | ADSP-21992YST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Mixed Signal DSP Controller With CAN |
| 中文描述： | 16-BIT, 100 MHz, OTHER DSP, PQFP176 |
| 封裝： | LQFP-176 |
| 文件頁數(shù)： | 3/49頁 |
| 文件大?。?/td> | 602K |
| 代理商： | ADSP-21992YST |
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog
Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
3
REV. PrA
For current information contact Analog Devices at (781) 937-1799
ADSP-21992
August 2002
PRELIMINARY TECHNICAL DATA
Architectural enhancements for compiled C code
efficiency
Architecture enhancements beyond ADSP-218x family
are supported with instruction set extensions for added
registers, ports, and peripherals.
The clock generator module of the ADSP-21992 includes
Clock Control logic that allows the user to select and change
the main clock frequency. The module generates two output
clocks; the DSP core clock, CCLK, and the peripheral
clock, HCLK. CCLK can sustain clock values of up to 160
MHz, while HCLK can be equal to CCLK or CCLK/2 for
values up to a maximum 80MHz peripheral clock.
The ADSP-21992 instruction set provides flexible data
moves and multifunction (one or two data moves with a
computation) instructions. Every single word instruction
can be executed in a single processor cycle. The
ADSP-21992 assembly language uses an algebraic syntax
for ease of coding and readability. A comprehensive set of
development tools supports program development.
The block diagram
Figure 1
shows the architecture of the
embedded ADSP-219x core. It contains three independent
computational units: the ALU, the multiplier/accumulator
(MAC), and the shifter. The computational units process
16-bit data from the register file and have provisions to
support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single
cycle multiply, multiply/add, and multiply/subtract opera-
tions. The MAC has two 40-bit accumulators, which help
with overflow. The shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations. The shifter can be used to efficiently implement
numeric format control, including multiword and block
floating point representations.
Register usage rules influence placement of input and
results within the computational units. For most operations,
the computational units’ data registers act as a data register
file, permitting any input or result register to provide input
to any unit for a computation. For feedback operations, the
computational units let the output (result) of any unit be
Figure 1. ADSP-21992 DSP Block Diagram
I/O REGISTERS
(MEMORY MAPPED)
CONTROL
STATUS
BUFFERS
I/O PROCESSOR
INTERRUPT CONTROLLER/
TIMERS/FLAGS
CACHE
64 X 24-BIT
JTAG
TEST &
EMULATION
ADDR BUS
MUX
EXTERNAL MEMORY
INTERFACE
EXTERNAL PORT
DATA BUS
MUX
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
ADSP-219X
DSP CORE
PROGRAM
SEQUENCER
DATA
REGISTER
FILE
MULT
BARREL
SHIFTER
ALU
DMA
CONTROLLER
INPUT
REGISTERS
RESULT
REGISTERS
16 X 16-BIT
AHB CORE
INTERFACE
DAG1
4 X 4 X 16
DAG2
4 X 4 X 16
DATA
DATA
ADDRESS
TWO INDEPENDENT BLOCKS
INTERNAL SRAM
ADDRESS
DMA
DATA
DMA
ADDRESS
EMBEDDED
CONTROL
PERIPHERALS AND
COMMUNICATIONS
PORTS
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